Back-End-of-Line Stacked Transistors for Dense Memory Cells
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in optimizing memory cell design to increase density and reduce latency while maintaining effective data storage and retrieval.
Innovation Solution
A memory device design featuring stacked transistors with controlled doping concentrations in the channel features and coplanar source/drain electrodes, allowing for reduced area occupation and improved threshold voltage control, fabricated in the back-end-of-line process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory cell design with two transistors is used, then data storage function is achieved, but memory density is limited and area occupation is high
Solution Approach 1:
The patent transitions from planar side-by-side transistor arrangement to a three-dimensional stacked configuration where the first transistor is positioned beneath the second transistor. This vertical stacking in the third dimension enables higher memory density without increasing the footprint area, directly resolving the contradiction between memory density and area occupation.
Solution Approach 2:
The stacked transistor structure embeds one transistor within the vertical space of another, with the first transistor's drain region nested beneath the second transistor's source region. This nesting approach maximizes space utilization and achieves higher density within the same area constraints.
2Quantity of substance
If stacked transistor structure is implemented, then memory density is increased, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory device into distinct functional layers: a first layer containing the first transistor with its source/drain regions, and a second layer containing the second transistor with its source/drain regions. This segmentation allows each layer to be fabricated and optimized independently while maintaining the overall stacked architecture, thereby managing manufacturing complexity.
Solution Approach 2:
The patent applies different doping concentrations to different regions of the channel features - the first channel feature has a first doping concentration while the second channel feature has a second doping concentration. This local differentiation optimizes the electrical characteristics of each transistor layer independently, simplifying the fabrication process by allowing separate doping steps for each layer.
3Manufacturing precision
If doping concentrations in channel features are optimized, then threshold voltage control is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent segments the doping process into separate steps for the first and second channel features. The first channel feature is doped with a first doping concentration in an initial step, and the second channel feature is doped with a second doping concentration in a subsequent step. This segmentation allows independent optimization of doping parameters for each layer, improving threshold voltage control while managing manufacturing precision requirements through staged processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances memory cell density and reduces memory latency by optimizing transistor structure and fabrication process, enabling efficient data storage and retrieval.
Implementation Method 1
the channel features have different doping concentrations
Data Source
AI summary
A memory device includes a first transistor and a second transistor. Each of the first and second transistors includes a first source/drain electrode, a second source/drain electrode, a channel feature, a gate dielectric and a gate electrode. The second source/drain electrode is coplanar with the first source/drain electrode. The channel feature is disposed between and interconnects the first and second source/drain electrodes. The gate dielectric is disposed over the channel feature. The gate electrode is disposed over the gate dielectric, and overlaps the channel feature. The second transistor is disposed over the first transistor. The first source/drain electrode of the second transistor is connected to the gate electrode of the first transistor.