BEOL Super Via Structure for Direct Multi-Level Interconnect Routing
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Solution Overview
Problem
Existing BEOL interconnect structures face challenges in efficient signal routing due to high resistance barriers and limited design flexibility, particularly in forming connections between conductive lines across multiple levels.
Innovation Solution
The implementation of super vias, which are formed using a subtractive etch process, allowing direct connections between conductive lines of different levels while bypassing intermediate levels, enabling the use of various conductive materials and combining subtractive and damascene techniques for customized formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BEOL interconnect structures with multiple intermediate levels are used, then design flexibility and material selection are limited, but high resistance barriers occur and signal routing efficiency decreases
Solution Approach 1:
The patent extracts and removes the intermediate dielectric layers (M2 ILD and M3 ILD) and intermediate conductive lines from the signal path by performing subtractive etching. This creates a direct super via connection from the first conductive line to the fourth conductive line, eliminating the high resistance barriers that would otherwise exist at multiple intermediate interfaces and improving signal routing efficiency
Solution Approach 2:
Instead of the conventional additive approach of building connections through multiple intermediate layers, the patent uses a subtractive approach by etching away intermediate layers to create direct connections. This inversion of the conventional formation method reduces resistance barriers and improves signal routing while maintaining design flexibility
2Adaptability or versatility
If subtractive etch process is used to form super vias, then design flexibility and material selection are enhanced, but additional manufacturing steps are required
Solution Approach 1:
The subtractive etch process creates universal compatibility with multiple conductive materials including copper, ruthenium, cobalt, and tungsten. The same etch process can form super vias regardless of the specific conductive material used in the first or fourth conductive lines, providing design flexibility and material versatility while maintaining a consistent manufacturing approach
Solution Approach 2:
The patent performs preliminary subtractive etching of the intermediate dielectric layers before forming the super via conductive material. This preliminary removal of M2 ILD and M3 ILD layers creates a direct path that simplifies subsequent super via formation and enables direct connection between non-adjacent conductive lines
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces high resistance barriers and enhances frequency performance by up to 2%, providing design flexibility and enabling the use of non-copper conductive materials like ruthenium, thus improving signal routing efficiency.
Implementation Method 1
subtractively etching a portion of a second interlevel dielectric layer and a portion of a third interlevel dielectric layer
Data Source
AI summary
Semiconductor devices including a super via connection between levels are provided. The semiconductor device can include a first interlevel dielectric layer, a back-end-of-line (BEOL) interconnect structure disposed in the first interlevel dielectric layer, a second interlevel dielectric layer disposed on a first portion of the first interlevel dielectric layer, a third interlevel dielectric layer disposed on the second interlevel dielectric layer, and a super via disposed on a second portion of the first interlevel dielectric layer, wherein a first end of the super via is connected to the BEOL interconnect structures and wherein a second end of the super via opposite the first end of the super via is a distance from the first interlevel dielectric layer larger than a height distance of the second interlevel dielectric layer.