BEOL Test Via Structure for EOS Detection in Semiconductor Fabrication
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Solution Overview
Problem
Semiconductor chips are prone to electrostatic over stress (EOS) damage during fabrication processes, leading to integration circuit failures, which are difficult to detect and correct.
Innovation Solution
A test structure is integrated into the back-end-of-line (BEOL) process to monitor and detect EOS damage, featuring a resistor-like design with varying via sizes and numbers to enhance sensitivity and detectability across different stages of chip fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fabrication processes are used without test structures, then manufacturing complexity is reduced, but EOS damage detection capability is lost
Solution Approach 1:
The patent segments the fabrication process into multiple stages (die level, package level, system level) with corresponding test structures at each stage. This allows EOS detection to be performed progressively without requiring complete redesign of the entire fabrication process, resolving the contradiction between detection capability and process complexity
Solution Approach 2:
Test structures are integrated into the BEOL process in advance, before final packaging and system assembly. This preliminary integration enables early detection of EOS damage, allowing corrective actions to be taken before further processing occurs, thus improving detection capability while maintaining process efficiency
2Reliability
If test structures are integrated into BEOL process, then EOS detection capability is improved, but manufacturing time is increased
Solution Approach 1:
The patent merges EOS detection functionality with existing BEOL interconnect structures by integrating test structures into the same fabrication流程. This consolidation allows detection functions to be added without requiring separate manufacturing cycles, thus improving reliability while minimizing time loss
Solution Approach 2:
The test structures are designed to automatically detect and indicate EOS damage through their inherent electrical characteristics during normal probing operations. This self-detecting capability eliminates the need for additional complex testing equipment or extended testing time, improving yield without significantly increasing manufacturing cycle time
3Measurement precision
If probe tests are performed at multiple stages, then EOS damage detection is enhanced, but testing complexity increases
Solution Approach 1:
The patent implements different test structure configurations optimized for specific detection stages: die-level tests use simple resistor-like structures, package-level tests use tower structures with varying via sizes, and system-level tests use full interconnect structures. This localized optimization allows each test to be simple and straightforward while collectively providing comprehensive EOS detection accuracy
Solution Approach 2:
The patent adds a temporal dimension to testing by performing probe tests at multiple sequential stages (die level → package level → system level) rather than a single stage. This multi-stage approach enhances detection accuracy by catching EOS damage at different points in the fabrication process, while each individual test remains relatively simple
Data Source
AI summary
A method for fabricating a semiconductor device is provided. The method includes forming a transistor over a semiconductor substrate; forming an interconnect structure including a test structure; forming conductive pads respectively electrically connected with nodes of the test structure, and performing a probe test on the conductive pads. A tower of the test structure connected between the two nodes includes at least one test metal via of a first via layer, at least one test metal via of a second via layer, and at least one test metal via of a third via layer. A size of the test metal via of the second via layer is less than a size of the test metal via of the third via layer, and a number of the test metal via of the second via layer is less than a number of the test metal via of the first via layer.