BEOL Thin Film Transistor Contacts Using Indium-Rich Features
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to the complexity introduced by miniaturization, which complicates the integration of various devices in semiconductor manufacturing.
Innovation Solution
The formation of a thin film transistor with an oxide semiconductor layer and indium-containing features in the back-end-of-line (BEOL) structure, which reduces contact resistance and Schottky barrier by connecting source/drain contacts through indium-rich features, allowing for improved device performance and reduced FEOL size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If miniaturization is pursued to improve production efficiency and lower costs, then productivity and manufacturing cost are improved, but device complexity and integration difficulty increase
Solution Approach 1:
The patent divides the transistor fabrication process into two distinct stages: FEOL (front-end-of-line) for forming the semiconductor substrate and basic transistor structures, and BEOL (back-end-of-line) for forming the thin film transistor structures. This segmentation allows each stage to be optimized independently, with BEOL processes operating at lower temperatures that do not compromise the FEOL structures, thereby managing integration complexity while maintaining productivity benefits from miniaturization
Solution Approach 2:
The patent introduces an intermediate layer structure between the FEOL substrate and the final thin film transistor, including gate dielectric layers, oxide semiconductor layers, and indium-containing features. These intermediate layers serve as mediators that enable the integration of BEOL processes at lower temperatures while maintaining electrical performance and preventing damage to underlying FEOL structures
2Reliability
If thin film transistor with oxide semiconductor layer is formed in BEOL, then contact resistance is reduced and device performance is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent applies local quality by forming indium-containing features specifically at the source/drain contact regions where low contact resistance is critical. The indium is selectively deposited in these localized areas rather than uniformly across the entire device, providing enhanced electrical performance at the contact interfaces while keeping the rest of the manufacturing process relatively simple and compatible with existing BEOL processes
3Temperature
If lower temperature manufacturing is used, then BEOL functionality is preserved, but manufacturing precision and material properties may be compromised
Solution Approach 1:
The patent employs parameter changes by carefully controlling the composition and thickness of oxide semiconductor layers and indium-containing features formed at lower temperatures. By adjusting deposition parameters, layer compositions, and subsequent annealing conditions, the patent achieves the desired material properties and electrical performance without requiring high-temperature processing that would damage BEOL structures
Data Source
AI summary
Semiconductor structures and methods for manufacturing the same are provided. The method for manufacturing the semiconductor structure includes forming a bottom electrode layer over a substrate and forming a gate dielectric layer over the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming an active layer over the gate dielectric layer and forming an indium-containing feature vertically overlapping the bottom electrode layer. The method for manufacturing the semiconductor structure also includes forming a source/drain contact landing on the indium-containing feature.