Vertical BEOL TFT Access Transistors for High-Current MRAM
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in providing sufficient drive current for memory technologies like MRAM, and they often occupy valuable space in the Front End of Line (FEOL) of a fabrication process, limiting integration density.
Innovation Solution
The integration scheme uses a plurality of vertical thin-film transistors (TFTs) connected in parallel as access transistors to provide a drive current for memory technologies. These TFTs are formed at low temperatures in the Back End of Line (BEOL) and are used in conjunction with Magnetic Tunnel Junction (MTJ) devices in a memory array, allowing for customization of device parameters and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If access transistors are formed in the Front End of Line (FEOL), then sufficient drive current for MRAM is achieved, but integration density is reduced due to occupation of valuable FEOL space
Solution Approach 1:
The patent moves the access transistor formation from the traditional planar FEOL process to the vertical BEOL process. By forming vertical TFTs in the interlayer dielectric layers above the substrate, the solution utilizes the third dimension (vertical stacking) to provide sufficient drive current for MRAM without occupying valuable horizontal FEOL space, thereby resolving the contradiction between drive current requirements and integration density.
2Area of stationary object
If vertical thin-film transistors are formed in the Back End of Line (BEOL) at low temperatures, then integration density is increased by freeing up FEOL space, but drive current capability must be maintained
Solution Approach 1:
The patent employs vertical TFT structures formed in BEOL interlayer dielectric layers, utilizing the vertical dimension to achieve high drive current capability without requiring additional horizontal space. The vertical orientation of the transistor channel allows sufficient current flow while freeing up FEOL area for increased integration density.
Solution Approach 2:
The patent modifies the transistor formation process by using low-temperature deposition techniques in the BEOL, changing the processing temperature parameter from high (typical FEOL) to low (BEOL compatible). This parameter change enables TFT formation in the BEOL while maintaining electrical performance sufficient for MRAM drive current requirements.
3Area of stationary object
If multiple memory stacks are integrated monolithically in the BEOL, then integration density is significantly increased, but manufacturing complexity increases
Solution Approach 1:
The patent divides the memory structure into multiple vertical stacks that are monolithically integrated in the BEOL. Each stack is formed as a separate vertical unit in the interlayer dielectric layers, allowing independent formation and connection. This segmentation enables high integration density while managing manufacturing complexity through modular vertical construction.
Solution Approach 2:
The patent combines multiple memory stacks into a single monolithic BEOL structure, merging separate memory units vertically. By integrating multiple stacks in the same BEOL region through shared interlayer dielectric layers and common processing steps, the patent achieves high integration density while reducing the overall device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher available drive currents for each MTJ of a MRAM cell, increases integration density by freeing up space in the FEOL, and allows for the formation of multi-stack memory arrays in the BEOL through monolithic integration.
Implementation Method 1
A MRAM cell typically includes a magnetic tunnel junction (MTJ) stack, which includes a pinned magnetic layer, a free magnetic layer, and a tunneling non-magnetic barrier layer between the pinned layer and the free layer
Data Source
AI summary
In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.