Self-Aligned BEOL TFT Active Regions for Precise N+ Doping
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Solution Overview
Problem
The semiconductor industry faces challenges in miniaturizing transistors beyond a certain limit, and transistors in the back-end-of-line (BEOL) position are vulnerable to ambient gases like hydrogen, which can degrade the channel region and make it difficult to control N+ doped region formation.
Innovation Solution
The implementation of self-aligned active regions and a self-aligned passivation layer to protect the channel region, using a metal oxide semiconductor approach that allows for low-temperature processing and incorporation of a self-aligned protection layer lining contact via structures, enabling precise doping and protection from ambient gases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are miniaturized to increase areal density, then productivity and areal density improve, but manufacturing precision and control over doped region formation deteriorate
Solution Approach 1:
A passivation layer is formed over the channel region before doping processes. This pre-formed layer serves as a mask and protection mechanism, enabling precise definition of N+ doped active regions while maintaining control during subsequent fabrication steps, thus resolving the precision loss associated with miniaturization
Solution Approach 2:
The passivation layer acts as an intermediary element between the channel region and the doping process. It enables controlled formation of N+ doped regions by serving as a protective barrier and alignment reference, allowing precise doping at scaled dimensions without compromising manufacturing control
2Adaptability or versatility
If transistors are placed in BEOL position to add functionality, then adaptability improves, but reliability deteriorates due to vulnerability to ambient gases
Solution Approach 1:
The passivation layer is formed in advance to prevent harmful effects of ambient gases (such as hydrogen) from reaching and degrading the channel region. This preliminary protective action counteracts the reliability issues that would otherwise arise from BEOL placement exposure to ambient environment
Solution Approach 2:
The passivation layer creates an inert protective environment over the channel region, isolating it from ambient gases. This protective barrier maintains channel integrity and reliability even when transistors are placed in BEOL positions where they would otherwise be exposed to degrading environmental conditions
3Ease of manufacture
If low-temperature processing is used for oxide semiconductor TFTs, then ease of manufacture improves, but manufacturing precision may deteriorate
Solution Approach 1:
The process replaces high-temperature thermal diffusion with ion implantation or low-temperature chemical vapor deposition methods to form N+ doped regions. The passivation layer serves as a precise mask during these low-temperature processes, enabling accurate doping control without requiring high temperatures, thus maintaining both ease of manufacture and precision
Data Source
AI summary
Field effect transistors and method of making. The field effect transistor includes a pair of active regions over a channel layer, a channel region formed in the channel layer and located between the pair of active regions, and a pair of contact via structures electrically connected to the pair of active regions. The contact via structure is formed in an interlayer dielectric layer that extends over the channel layer.