BEOL-Compatible Thin Film Transistor Contact Liner Structure
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving cost-effective 3D integration of BEOL compatible components, particularly in the integration of thin-film transistors, which are not efficiently integrated with standard BEOL processing steps.
Innovation Solution
A method for fabricating thin film transistors that are compatible with BEOL processing, involving the use of a gate metal, gate dielectric layer, semiconductor layer, interlayer dielectric, and source/drain structures, with specific materials and processing steps such as CVD and etching to create a flexible design for channel formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If thin film transistors are integrated using standard BEOL processing steps, then manufacturing cost is reduced and ease of manufacture is improved, but device complexity increases due to the need for BEOL compatible materials and processes
Solution Approach 1:
The patent applies universality by designing a thin film transistor structure that can be manufactured using standard BEOL processing steps. The gate electrode uses materials like TiN or TaN that are compatible with existing BEOL toolsets, and the multi-layer structure (including liner layers, barrier layers, and interlayer dielectric) is designed to integrate with standard BEOL interconnect processes, allowing the same fabrication infrastructure to produce both interconnects and active devices
Solution Approach 2:
The patent segments the transistor structure into distinct functional layers that can be processed independently using standard BEOL steps. The gate electrode is separated from source/drain regions by interlayer dielectric, and each layer (liner, barrier, conductive fill, dielectric) can be deposited and patterned using existing BEOL processes, enabling modular manufacturing
2Productivity
If thin film transistors are fabricated with BEOL compatible materials and processes, then productivity is improved through streamlined manufacturing, but manufacturing precision may be compromised due to process compatibility constraints
Solution Approach 1:
The patent employs parameter changes by adjusting material properties and process parameters to achieve both BEOL compatibility and high precision. For example, the gate electrode thickness is controlled within specific ranges (e.g., 50-200 nm), the interlayer dielectric thickness is optimized (e.g., 100-500 nm), and deposition conditions are tuned to achieve precise film thicknesses and compositions that meet both productivity and precision requirements
Solution Approach 2:
The patent uses composite material structures to achieve precision while maintaining BEOL compatibility. The gate electrode employs multi-layer compositions (e.g., TiN/TaN, or TiN with liner layers), and the interlayer dielectric includes composite structures with liner layers and barrier layers. These composite structures provide precise electrical and mechanical properties that can be controlled through standard BEOL processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables cost-effective integration of thin film transistors within BEOL wiring levels, enhancing 3D integration capabilities and ensuring desirable electrical performance through controlled channel design and hydrogen barrier properties.
Implementation Method 1
processing steps such as CVD and etching
Implementation Method 2
processing steps such as CVD and etching
Data Source
AI summary
A thin film transistor, a semiconductor device having a thin film transistor and a method of fabricating a thin film transistor are provided. The thin film transistor includes a gate metal; a gate dielectric layer disposed on the gate metal; a semiconductor layer disposed on the gate dielectric layer; an interlayer dielectric disposed on the semiconductor layer and having a contact hole over the semiconductor layer; a source/drain metal disposed in the contact hole; a first liner disposed between the interlayer dielectric and the source/drain metal; and a second liner disposed between the first liner and the source/drain metal and being in contact with the semiconductor layer in the contact hole.