BEOL Thin-Film Transistor Isolation Structure for Low-Temperature Integration
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Solution Overview
Problem
The semiconductor industry faces challenges in further increasing integration density without damaging existing devices, particularly in the back-end-of-line (BEOL) integration of thin-film transistors, which require new materials and processes that can operate at low temperatures to avoid damaging front-end-of-line (FEOL) and middle end-of-line (MEOL) devices.
Innovation Solution
A thin-film transistor structure is developed using a gate electrode embedded in an etch stop layer and dielectric layer, with a gate dielectric layer, an active layer made of oxide semiconductor materials, and source/drain features surrounded by an isolation structure that includes a blocking layer to prevent diffusion of unwanted elements and maintain carrier concentration, allowing for low-temperature processing without damaging existing devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature processes are used to fabricate transistors, then device performance is improved, but previously fabricated FEOL and MEOL devices are damaged
Solution Approach 1:
The patent changes the temperature parameter of the fabrication process from high-temperature to low-temperature processing. The thin-film transistor is fabricated using processes conducted at temperatures below 400°C, which maintains device performance while preventing damage to previously fabricated FEOL and MEOL devices that cannot withstand high temperatures.
Solution Approach 2:
The patent performs the thin-film transistor fabrication in the BEOL stage after FEOL and MEOL devices have already been fabricated and are in place. This preliminary action sequence ensures that temperature-sensitive previously fabricated devices are not exposed to damaging high-temperature processes, while still achieving the desired device performance through low-temperature fabrication techniques.
2Productivity
If integration density is increased by reducing feature size, then more components can be integrated, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different material compositions and processing conditions to different regions of the transistor structure. The active layer uses specific oxide semiconductor compositions with controlled stoichiometry, while the gate electrode uses particular metal combinations. This local quality approach enables precise control of electrical properties and device performance even at reduced feature sizes, maintaining manufacturing precision while increasing integration density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the integration of thin-film transistors in the BEOL process without damaging FEOL and MEOL devices, improving electrical performance and reliability by stabilizing carrier concentration and preventing chemical contamination.
Implementation Method 1
a blocking layer to protect the active layer from unwanted element diffusion
Implementation Method 2
an isolation structure to maintain electrical performance and reliability
Data Source
AI summary
Provided are a transistor structure and a method of forming the same. The transistor structure includes a gate electrode; a gate dielectric layer, disposed on the gate electrode; an active layer, disposed on the gate dielectric layer; a pair of source/drain (S/D) features, disposed on the active layer; and an isolation structure, laterally surrounding the pair of S/D features, wherein the isolation structure at least comprises a blocking layer and an upper dielectric layer on the blocking layer.