BEOL Single Crystalline Transistors via Metal-Assisted Epitaxy
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Solution Overview
Problem
Current semiconductor device manufacturing techniques face challenges in increasing device integration density and performance while reducing power consumption and footprint, particularly in the back end of line (BEOL) process, where traditional methods are complex and costly.
Innovation Solution
The integration of single crystalline transistors using a monocrystalline semiconductor layer formed on a conductive layer within an insulating layer, employing metal-assisted single crystal epitaxy growth to create high-quality transistors with reduced defects, thereby enhancing device performance and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional 3D IC fabrication techniques are used to increase device integration density, then vertical interconnection is achieved, but the integration process becomes complicated and costly
Solution Approach 1:
The patent transitions from conventional planar transistor integration to vertical 3D integration by forming transistor channels in the vertical direction through trenches in the interlayer dielectric. Multiple transistor stacks are arranged vertically, enabling higher device integration density while maintaining a compact footprint and simplifying the integration process compared to traditional 3D IC techniques
Solution Approach 2:
The patent divides the interlayer dielectric into multiple levels with trenches formed at different depths, allowing independent formation and interconnection of transistor stacks at various vertical levels. This segmentation enables modular integration, reducing overall process complexity while achieving high device density through systematic vertical stacking
2Quantity of substance
If device dimensions are decreased to increase integration density, then more devices fit on the chip, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the dimensional parameters of transistor structures by forming vertical channels through deep trenches rather than shrinking planar dimensions. This parameter transformation allows high device density to be achieved through vertical stacking rather than lateral miniaturization, thereby reducing the stringent manufacturing precision requirements associated with sub-10nm planar transistors
3Use of energy by moving object
If power consumption is reduced through smaller device dimensions, then energy efficiency improves, but device performance may deteriorate
Solution Approach 1:
The patent achieves power reduction not by shrinking device dimensions but by increasing integration density through vertical stacking. This dimensional transition allows more devices to operate in parallel at moderate dimensions, maintaining individual device performance while improving overall system energy efficiency through higher operational throughput and reduced per-operation energy consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device performance, increased density, reduced power consumption, and a smaller footprint compared to conventional techniques, with better quality transistors and reduced defects in the BEOL process.
Implementation Method 1
employing metal-assisted single crystal epitaxy growth to create high-quality transistors with reduced defects
Data Source
AI summary
A monocrystalline semiconductor layer is formed on a conductive layer on an insulating layer on a substrate. The conductive layer is a part of an interconnect layer. The monocrystalline semiconductor layer extends laterally on the insulating layer. Other embodiments may be described and/or claimed.