BEOL Trench RRAM Structure for High-Density Thin Via Layers
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Solution Overview
Problem
Current methods for integrating Resistive Random-Access Memory (RRAM) in the Back End of Line (BEOL) face challenges due to the difficulty in fitting RRAM structures in thinner via layers, leading to limited density and manufacturing issues, especially in regions with high-density and tight pitch interconnections.
Innovation Solution
The implementation of RRAM with an internal electrode surrounded by a high k dielectric layer, disposed within a trench in the substrate, and connected to interconnects, allowing for electrical contact and forming a trench structure that accommodates RRAM arrays in thinner BEOL layers, enabling higher density arrays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If RRAM structures are placed in upper thick metal levels, then device height requirements are met, but RRAM array density is reduced due to large interconnect pitches
Solution Approach 1:
The patent transitions from planar RRAM placement to three-dimensional trench structures. By etching trenches into the substrate and placing RRAM devices vertically within these trenches, the design utilizes the vertical dimension to increase device density without being constrained by the horizontal interconnect pitch in upper metal levels
Solution Approach 2:
The RRAM structures are nested within trenches that are formed in the substrate. The trench structure allows multiple RRAM devices to be stacked vertically, with each device contained within the trench cavity, effectively nesting the RRAM array within the substrate volume rather than spreading it across large surface areas
2Quantity of substance
If RRAM structures are placed in lower thin via layers, then RRAM array density is increased, but device fabrication becomes infeasible due to process limitations
Solution Approach 1:
The patent modifies the substrate properties by forming trenches with specific depth and width parameters. These trenches create localized regions with adjusted physical dimensions that accommodate RRAM devices while maintaining compatibility with standard BEOL fabrication processes. The trench depth and cross-sectional dimensions are carefully controlled to enable device formation in lower substrate levels without requiring advanced manufacturing capabilities
3Loss of energy
If via layers are made thinner to reduce resistive power losses, then power efficiency is improved, but the ability to fit taller RRAM components is reduced
Solution Approach 1:
Instead of increasing via layer thickness horizontally, the patent utilizes the vertical dimension by creating trenches that extend deeper into the substrate. This allows RRAM devices to achieve their required height within the vertical space of the trench while maintaining thin via layer thicknesses for reduced resistive losses
Solution Approach 2:
The via layer structure is segmented into multiple sections: thin via layers for power distribution to minimize resistive losses, and deeper trench structures for accommodating RRAM device heights. This segmentation allows each layer to be optimized for its specific function without compromise
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful integration of high-density RRAM arrays in thinner BEOL layers, overcoming topographical challenges and manufacturing difficulties, thereby enhancing the density and reliability of RRAM arrays.
Implementation Method 1
A dielectric, which is normally insulating, can be made to conduct (in a low resistance state (LRS)) through one or more filaments or conduction paths formed by application of a sufficiently high voltage
Data Source
AI summary
A Resistive Random-Access Memory (RRAM) has an internal electrode; a high k dielectric layer surrounding and in contact with the internal electrode; a lower substrate; and a trench having three or more trench sides disposed within the lower substrate; and one or more interconnects each with an interconnect side. The interconnect side forms part of one of the trench sides. The internal electrode and the high k dielectric layer are disposed within the trench with the interconnect side in contact with the high k dielectric layer. In some embodiments, an external electrode is between and electrically connected to the high k dielectric layer and the internal electrode. The external electrode then forms the electrical connection between the high k dielectric and the interconnect side. Multiple embodiments are disclosed including RRAMs created in multiple substrates; different RRAM configurations; and dual, three-wire RRAMs with two interconnects. Arrays of RRAMs and methods of making are also disclosed.