BEOL Conductive Via Structure Using Single-Step Aluminum Sputtering
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Solution Overview
Problem
Conventional BEOL manufacturing processes for semiconductor devices involve complex steps, material wastage, and increased resistance due to the use of tungsten material, which affects chip size shrinkage and electrical performance.
Innovation Solution
A semiconductor structure is developed with a second metal line that extends into a through hole, eliminating the need for tungsten deposition and polishing, and is formed by a single sputtering step, using materials like aluminum for improved conductivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tungsten material is used to form conductive via through deposition and CMP polishing, then the via can be formed to connect metal lines, but the process complexity increases and material wastage occurs
Solution Approach 1:
The patent merges the conductive via formation and the second metal line formation into a single aluminum deposition process. The aluminum layer is patterned to simultaneously create the via structure and the metal line, eliminating the need for separate tungsten deposition and CMP polishing steps. This reduces process complexity while maintaining electrical connection reliability between metal lines.
2Manufacturing precision
If tungsten material is polished by CMP to form conductive via, then the via shape is refined, but most of the tungsten material is wasted
Solution Approach 1:
The patent changes the material parameter from tungsten to aluminum for the conductive via. Aluminum can be directly deposited and patterned without requiring CMP polishing to achieve the desired via shape, thereby eliminating material wastage while maintaining manufacturing precision. The aluminum material properties allow for direct patterning to form precise via structures.
3Reliability
If tungsten material is used for conductive via, then the via can be formed, but the conductivity is not good and resistance is increased
Solution Approach 1:
The patent changes the material parameter from tungsten to aluminum for the conductive via and second metal line. Aluminum has superior electrical conductivity compared to tungsten, which reduces electrical resistance and energy loss in the interconnect structure. This material substitution directly improves electrical connection reliability while reducing resistive losses.
4Reliability
If multiple manufacturing steps including deposition and CMP are used to form conductive via, then the via structure is created, but the cycle time is increased
Solution Approach 1:
The patent combines multiple manufacturing steps into a single aluminum deposition and patterning process. Instead of separate tungsten deposition, via formation, and CMP polishing steps, the aluminum layer is deposited and patterned in one sequence to simultaneously create the conductive via and the second metal line. This merging of operations significantly reduces manufacturing cycle time while maintaining via formation reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material costs, cycle time, and resistance, enhancing the process window for chip size shrinkage by utilizing a single-material conductive via.
Implementation Method 1
The first buffer layer, the second metal line, and the second buffer layer are formed by sputtering
Data Source
AI summary
A semiconductor structure includes a first dielectric layer, a protection layer, a second dielectric layer, a first buffer layer, and a second metal line. The first dielectric layer has a first metal line in a top surface of the first dielectric layer. The protection layer is located on the first dielectric layer. The second dielectric layer is located on the protection layer, wherein the second dielectric layer and the protection layer have a through hole, and the first metal line is below the through hole. The first buffer layer is located on a top surface of the second dielectric layer, a sidewall of the through hole, and a top surface of the first metal line. The second metal line is located on the first buffer layer and extends into the through hole.