BEOL Interconnect Via Structure Without Etch-Stop Layers
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Solution Overview
Problem
As semiconductor feature sizes decrease, the complexity of BEOL interconnect structure fabrication increases, leading to challenges such as misalignment issues during via formation, overlay shift, and the formation of tiger-tooth profiles, which result in electrical leakage and capacitance issues due to the need for complex etch-stop layers.
Innovation Solution
An etch-free via-forming method is introduced, where via openings are formed without etching the dielectric layer, eliminating the requirement for etch-stop layers and simplifying overlay control, thereby mitigating misalignment and tiger-tooth issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching methods are used to form via openings, then via formation is achieved, but misalignment issues and overlay shift occur
Solution Approach 1:
The patent extracts and removes the etching step from the via formation process. Instead of etching through the dielectric layer to form via openings, the method uses a deposition-based approach where conductive material is deposited to form vias directly, eliminating the etching process and its associated alignment and overlay issues.
Solution Approach 2:
The patent inverts the traditional via formation sequence. Rather than etching holes first and then filling them with conductive material, the method deposits conductive material to form vias directly on the dielectric surface, fundamentally reversing the conventional approach and eliminating etching-related problems.
2Reliability
If etch-stop layers are used to prevent tiger-tooth profiles, then via formation is achieved, but electrical leakage and capacitance issues arise
Solution Approach 1:
The patent extracts and eliminates the etch-stop layer from the structure. By removing the etching process entirely and using deposition to form vias, the need for etch-stop layers is eliminated, thereby removing the source of electrical leakage and capacitance issues associated with these layers.
Solution Approach 2:
The patent converts the harmful effect of complex etch-stop layer structures (which cause electrical leakage and capacitance issues) into a beneficial simple deposition process. The harmful complexity of multiple etch-stop layers is transformed into the benefit of a straightforward material deposition approach that forms vias without requiring etch-stop layers.
3Productivity
If feature sizes are decreased to increase functional density, then production efficiency is improved, but fabrication difficulty increases
Solution Approach 1:
The patent replaces the mechanical/chemical etching process with a deposition-based formation process. This substitution eliminates the complexity of controlling etching at small feature sizes, where alignment and overlay become increasingly difficult, thereby maintaining ease of manufacture even as functional density increases through smaller features.
Data Source
AI summary
A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.