BEOL Interconnect Via Structure With Etch-Free Overlay Control
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Solution Overview
Problem
As semiconductor feature sizes continue to shrink, the complexity of BEOL interconnect structure fabrication increases, leading to challenges such as misalignment issues during via formation, which result in electrical leakage paths and capacitance problems due to the need for complex etch-stop layers.
Innovation Solution
An etch-free via-forming method is introduced, where via openings are formed without etching the dielectric layer, eliminating the requirement for etch-stop layers and simplifying overlay control, thus mitigating overlay shift and tiger-tooth issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching methods are used to form via openings, then via formation can be achieved, but misalignment issues occur and electrical leakage paths are created
Solution Approach 1:
The patent removes the etching process entirely from via formation, extracting the harmful etching step that causes misalignment and electrical leakage. Instead of etching through the dielectric layer, the invention uses a deposition-based approach where metal is deposited to form the via structure directly, eliminating the source of alignment errors and leakage paths.
Solution Approach 2:
The patent inverts the conventional via formation approach by depositing material to build the via structure upward rather than etching downward to create the via. This inversion of the formation method fundamentally changes the process from a subtractive etching approach to an additive deposition approach, resolving the alignment and leakage issues.
2Reliability
If complex etch-stop layers are added to prevent electrical leakage, then reliability improves, but device complexity increases
Solution Approach 1:
The patent extracts and removes the entire etch-stop layer structure from the via formation process. By eliminating the etching process, the need for etch-stop layers is completely removed, simplifying the device structure while maintaining reliability through the alternative deposition-based via formation method.
3Manufacturing precision
If traditional via formation processes are used, then via structures can be created, but overlay control becomes difficult and overlay shift occurs
Solution Approach 1:
The patent removes the etching step that creates overlay control difficulties. By replacing etching with deposition, the process eliminates the need for precise etch alignment and stop-layer management, significantly improving overlay control while simplifying the fabrication process.
Data Source
AI summary
A semiconductor structure includes a first metallization feature, a first dielectric structure over the first metallization feature, a second metallization feature embedded in the first dielectric structure, a via structure between the first metallization feature and the second metallization feature, and a first insulating layer between the first dielectric structure and the first metallization feature, and between the first dielectric structure and the via structure. The first metallization feature extends along a first direction, and the second metallization feature extends along a second direction different from the first direction. The first insulating layer covers first sidewalls of the via structure along the second direction.