2D Self-Aligned BEOL Vias With Subtractive Metal Etch
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Solution Overview
Problem
The complexity of layer formation and etch operations in microelectronic device fabrication, particularly in back end of line (BEOL) processes, has made it challenging to achieve accurate alignment and precision in etching operations as device features become smaller and more complex.
Innovation Solution
A method involving the deposition of oxide layers and hard masks, followed by etching and gap-filling processes, is used to form vias that connect metal layers with improved alignment and accuracy, utilizing a 2-dimensional self-aligned scheme with subtractive metal etch techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching operations are used in BEOL processes, then the manufacturing process is simpler, but the alignment accuracy and precision of etching operations deteriorate as device features become smaller
Solution Approach 1:
The etching process is divided into multiple sequential steps: first etching through the first oxide layer and hard mask to form a first portion of the via, then etching through the upper metal layer and low-k material layers to form a second portion of the via. This segmentation allows each etching step to be optimized independently for precision and alignment, resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The first oxide layer is deposited and patterned before the etching operations begin, creating a preliminary structure that guides subsequent etching steps. The hard mask layer is also prepared in advance with precise patterns that serve as alignment references for the via etching, ensuring high alignment accuracy before the actual etching commences.
2Area of moving object
If device feature size is reduced to achieve higher integration, then device density increases, but alignment difficulty and etching precision worsen
Solution Approach 1:
The first oxide layer serves as an intermediary layer between the hard mask and the underlying structures. It provides a buffer zone that allows for precise alignment of the via etching relative to the hard mask features, while also protecting the hard mask during processing. This intermediary structure enables accurate alignment even as feature sizes are reduced.
Solution Approach 2:
The patent introduces vertical layering with multiple oxide layers and metal layers at different heights, creating a three-dimensional structure that allows alignment to be achieved through vertical stacking rather than relying solely on planar alignment. The self-aligned nature of the process uses the vertical dimension to ensure precise horizontal alignment of features.
3Productivity
If via dimensions are reduced for higher density interconnects, then device capacity increases, but gap-filling and alignment become more difficult
Solution Approach 1:
The gap fill metal is deposited selectively to fill only the via regions, with the deposition process optimized for the specific geometry and dimensions of each via. The low-k material layers provide a controlled environment that facilitates uniform gap filling even in high-density interconnect structures with varying via dimensions.
Solution Approach 2:
The via etching is performed to precise dimensions before gap filling, creating well-defined via openings that are optimized for subsequent gap fill deposition. The first and second oxide layers are prepared in advance to provide proper spacing and alignment references, making the gap-filling process more manageable despite reduced via dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables precise alignment and connection of metal layers with reduced interconnect width, enhancing the accuracy and complexity of device structures in microelectronic devices, particularly at ultra-small pitch patterning scales.
Implementation Method 1
depositing a first oxide layer over a patterned hard mask layer
Implementation Method 2
Plasma dry etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers
Data Source
AI summary
Methods for formation of a layer stack during a back-end-of-line (BEOL) process flow and the layer stack formed therefrom are provided. In one or more embodiments, the method utilizes a two-dimensional (2D) self-aligned scheme with a subtractive metal etch. The method includes using a hard mask to form a via with a small width which is formed through or contacts each of a first metal layer and a second metal layer. The via is filled with a metal gapfill to connect the first metal layer and the second metal layer. Each of the first metal layer and the second metal layer are patterned to form a plurality of features.