Self-Aligned BEOL Vias Using Sacrificial Patterning to Cut RC Delay
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in achieving precise alignment and reducing misalignment between vias and underlying electrically conductive structures, particularly at small scales, which affects BEOL resistance-capacitance (RC) delays and overall reliability of integrated circuits.
Innovation Solution
The method involves forming self-aligned vias in the BEOL by patterning a sacrificial material and top dielectric material to create openings for both bottom and top metal lines, using etch block materials for selective etching, and depositing conductive materials to ensure precise alignment and minimize misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via alignment methods are used, then manufacturing process is simpler, but misalignment between vias and metal lines increases
Solution Approach 1:
The patent applies preliminary action by forming sacrificial structures (mandrels) that define the via locations before the actual via formation process. These sacrificial structures are created during the metal line patterning process, ensuring that via openings will automatically align with the metal lines. This preliminary positioning action eliminates the need for separate alignment processes and achieves self-alignment.
Solution Approach 2:
The patent uses sacrificial materials (mandrels) as intermediary structures that facilitate the alignment process. These temporary structures are formed first, then used as templates for via opening formation, and finally removed after via filling. The intermediary sacrificial structures enable precise via placement without requiring complex direct alignment methods.
2Area of moving object
If via size is reduced for higher density, then interconnect density increases, but alignment precision becomes more difficult to achieve
Solution Approach 1:
The patent implements self-service through self-aligned via formation where the via openings automatically position themselves relative to the metal lines using the sacrificial structures as references. The process is self-aligning because the same sacrificial structures that define metal line positions also define via positions, eliminating the need for external alignment interventions and maintaining precision even at reduced via sizes.
Solution Approach 2:
By pre-forming sacrificial structures at the desired via locations during the metal line patterning process, the patent establishes precise via positions before via formation begins. This preliminary action ensures that even when via dimensions are reduced for higher density, the alignment precision is maintained because the via locations are predetermined by the sacrificial structures.
3Reliability
If misalignment between vias and metal lines is not minimized, then RC delays increase, but reducing misalignment requires more complex processes
Solution Approach 1:
The sacrificial structures serve as intermediary elements that ensure precise via-to-metal-line alignment, thereby minimizing RC delays. These intermediaries are formed as part of the standard patterning process and automatically provide the alignment function without requiring additional complex alignment steps, thus improving reliability without proportionally increasing process complexity.
Solution Approach 2:
By performing preliminary patterning to create sacrificial structures that define both metal line and via positions, the patent minimizes misalignment and associated RC delays. This preliminary action is integrated into the existing fabrication process flow, achieving improved electrical connectivity reliability without requiring separate complex alignment processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces misalignment, decreases RC delays, and enhances the reliability of IC structures by maximizing area overlap between vias and metal lines, thereby improving electrical connectivity and performance.
Implementation Method 1
using etch block materials for selective etching
Implementation Method 2
depositing conductive materials to ensure precise alignment and minimize misalignment
Data Source
AI summary
Disclosed herein are methods for manufacturing an integrated circuit (IC) structure, e.g., for manufacturing a metallization stack portion of an IC structure, with one or more self-aligned vias integrated in the back end of line (BEOL), and related semiconductor devices. The methods may employ direct metal etch for scaling the BEOL pitches of the metallization layers. In one aspect, an example method results in fabrication of a via that is self-aligned to both a metal line above it and a metal line below it. Methods described herein may provide improvements in terms of one or more of reducing the misalignment between vias and electrically conductive structures connected thereto, reducing the RC delays, and increasing reliability if the final IC structures.