BEOL Wiring Structures with Embedded Active Devices
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Solution Overview
Problem
Current integrated circuit (IC) manufacturing faces challenges in increasing circuit density and yield while maintaining performance and reducing costs, particularly in the back-end-of-line (BEOL) processing, where the use of low-k dielectrics and porous materials leads to mechanical weakness and signal degradation, and the stacking of 3D ICs results in high costs and low bonding yields.
Innovation Solution
The integration of semiconductor active and nonlinear devices within the BEOL wiring levels on a single substrate, using damascene Cu wiring levels in low-κ dielectrics with tensile stress, and employing silicon nitride or silicon carbonitride layers to enhance mechanical strength and minimize substrate curvature, eliminating the need for bonding interfaces and separate substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-k dielectrics and porous materials are used in BEOL processing, then signal performance is improved, but mechanical strength deteriorates
Solution Approach 1:
The patent employs a composite structure combining low-k dielectric materials with porous filler materials (such as spinel, perovskite, or rock salt structures) to create a mechanically strengthened BEOL layer. This composite approach maintains the low dielectric constant for signal performance while the porous filler provides mechanical support and prevents stress-induced defects.
2Productivity
If 3D IC stacking is implemented, then circuit density is increased, but manufacturing cost increases and bonding yield decreases
Solution Approach 1:
The patent transitions from traditional planar 2D IC architecture to a 3D stacked architecture by vertically stacking multiple active device layers separated by BEOL interconnect layers. This dimensional change enables increased circuit density without proportionally increasing manufacturing complexity, as the stacking is achieved through integrated fabrication processes rather than separate bonding steps.
3Adaptability or versatility
If multiple separate substrates are bonded together for 3D IC, then device functionality is increased, but bonding yield decreases and cost increases
Solution Approach 1:
The patent merges multiple active device layers and BEOL interconnect layers into a single monolithic substrate structure, eliminating the need for separate substrate bonding. This integration approach maintains device functionality while avoiding bonding-related yield losses and cost increases associated with wafer bonding, adhesive layers, and alignment processes.
4Productivity
If active devices are integrated within BEOL wiring levels, then circuit density is increased, but mechanical stress management becomes more difficult
Solution Approach 1:
The patent applies local quality by selectively placing porous filler materials in specific regions of the BEOL structure where mechanical support is needed, while maintaining low-k dielectric properties in other regions for optimal signal performance. This localized approach allows stress management without compromising overall circuit density or electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a monolithic integrated circuit with increased circuit density, improved mechanical strength, and enhanced reliability, reducing manufacturing costs and maintaining signal performance, as the active devices are embedded within the wiring layers, eliminating the need for separate bonding and increasing the overall yield.
Implementation Method 1
employing silicon nitride or silicon carbonitride layers to enhance mechanical strength and minimize substrate curvature
Data Source
AI summary
An integrated circuit and method includes a substrate, a plurality of semiconductor device layers monolithically integrated on the substrate, and a metal wiring layer with vias interconnecting the plurality of semiconductor device layers. The semiconductor device layers are devoid of bonding or joining interface with the substrate.