BEOL Wiring Pitch Layout for Dense Contacts and Power Routing
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Solution Overview
Problem
Current semiconductor technologies face challenges in reducing the size of structural features and increasing the density of features within a given chip size, while maintaining performance and reducing power consumption.
Innovation Solution
The technique involves forming middle back-end-of-line (BEOL) wiring layers with different pitches, where the uppermost and lowermost interconnect wiring levels have a smaller pitch, and the intermediate levels have a larger pitch, allowing for efficient connections and power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If uniform pitch is used across all interconnect wiring levels, then manufacturing process is simpler, but feature density and chip performance are limited
Solution Approach 1:
The interconnect wiring structure is segmented into multiple levels with different pitch characteristics. Uppermost and lowermost levels use first pitch for high-density connections to device layers, while intermediate levels use second pitch for power delivery and signal routing. This segmentation allows each layer to be optimized for its specific function, increasing overall feature density without requiring complete redesign of the entire wiring system.
Solution Approach 2:
Different regions of the wiring structure are assigned different pitch values based on local functional requirements. The uppermost and lowermost interconnect levels have smaller pitch (first pitch) to achieve high-density connections to the first and second device layers, while intermediate levels have larger pitch (second pitch) suitable for power delivery and global routing. This local differentiation optimizes performance for each specific wiring level's function.
2Manufacturing precision
If smaller pitch is used in all wiring levels, then feature density increases, but manufacturing precision requirements and process difficulty increase
Solution Approach 1:
Instead of applying the smallest pitch uniformly across all wiring levels, the invention applies small pitch (first pitch) only where it is most critical - at the uppermost and lowermost levels that directly connect to device layers. Intermediate levels use larger pitch (second pitch) where high precision is less critical, thereby reducing overall manufacturing difficulty while maintaining the necessary precision at critical interfaces.
3Ease of manufacture
If larger pitch is used in all wiring levels, then manufacturing is easier, but feature density and chip size reduction are limited
Solution Approach 1:
The wiring structure is divided into segments with different pitch values. The uppermost and lowermost levels use small first pitch to maximize area utilization and feature density where connections to device layers are required. Intermediate levels use larger second pitch for easier manufacturing and power delivery functions. This segmentation achieves high area utilization without requiring the entire wiring system to use the smallest, most difficult-to-manufacture pitch.
Data Source
AI summary
A semiconductor structure comprises a first device layer, a second device layer, and a plurality of interconnect wiring levels between the first device layer and the second device layer. The plurality of interconnect wiring levels comprise a first interconnect wiring level adjacent the first device layer, wherein wires of the first interconnect wiring level are spaced apart from each other at a first pitch, a second interconnect wiring level adjacent the second device layer, wherein wires of the second interconnect wiring level are spaced apart from each other at a second pitch, and at least a third interconnect wiring level between the first interconnect wiring level and the second interconnect wiring level, wherein wires of the third interconnect wiring level are spaced apart from each other at a third pitch. The third pitch is greater than the first pitch and the second pitch.