BEOL Wiring Structure With Sidewall Insulation for Lower RC Delay
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Solution Overview
Problem
The increasing speed requirements of complementary metal oxide semiconductors (CMOSs) and logic devices are hindered by gate delay times due to resistance-capacitance (RC) delays in metal wirings of the back end of line (BEOL) in high-integration semiconductor devices.
Innovation Solution
The integrated circuit device incorporates a substrate with wiring structures, insulating patterns, capping layers, and interlayer insulating layers, featuring specific materials like SiO2, Al2O3, graphene, and low-k materials to optimize wiring geometry and reduce RC delays, including a via layer connected to the wiring structures and interlayer insulating layers with upper surfaces higher than the wiring and insulating patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the length of gate is reduced to reduce gate delay time, then device speed is improved, but RC delay due to metal wirings becomes the limiting factor
Solution Approach 1:
The patent changes the physical parameters of the wiring structure by forming insulating patterns on sidewalls of wiring layers and adding capping layers. This modifies the geometric parameters (width, height, spacing) and material parameters (dielectric constant through low-k materials) to reduce RC delay. The insulating patterns reduce capacitance between adjacent wiring layers, while the capping layers optimize the wiring geometry to minimize resistance, thereby reducing the overall RC delay and improving device speed.
2Reliability
If insulating patterns are formed on sidewalls of wiring layers, then capacitance between wiring layers is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the insulating structure into two distinct parts: insulating patterns formed on the sidewalls of wiring layers, and separate capping layers formed on top of the wiring layers. This segmentation allows each component to be optimized independently - the sidewall insulating patterns reduce inter-layer capacitance, while the capping layers provide planarization and protection. The segmented approach manages manufacturing complexity by breaking down a complex 3D insulating structure into simpler, more controllable formation steps.
3Manufacturing precision
If capping layers are formed on wiring layers, then wiring geometry is optimized, but etching process complexity increases
Solution Approach 1:
The patent introduces capping layers as intermediary structures between the wiring layers and the overlying interlayer insulating layers. These capping layers serve as etch stop layers and etch masks, mediating the etching processes that follow. By providing a dedicated etch stop function, the capping layers simplify the overall etching process control, allowing for more precise wiring geometry formation while managing the complexity of multi-layer etching through selective etch stops.
Data Source
AI summary
An integrated circuit device includes a plurality of wiring structures on a substrate and extending in a first direction parallel to an upper surface of the substrate and each including a wiring layer on the substrate and extending in a direction perpendicular to the upper surface of the substrate; an insulating pattern surrounding a sidewall of the wiring layer and including a first insulating material; and a capping layer on an upper surface of the wiring layer and including a conductive material; a via layer on the wiring structures, the via layer being electrically connected to one wiring structure; and an interlayer insulating layer covering a sidewall of the insulating pattern between each wiring structure of the plurality of wiring structures, the interlayer insulating layer having an upper surface higher than an upper surface of each wiring layer and an upper surface of each insulating pattern.