Generic Bit Error Rate Analyzer for Serial Data Links
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Solution Overview
Problem
Existing bit error rate analyzers face challenges such as being prohibitively costly, unable to test single channel protocols like USB 2.0, and increasing area overhead for multiple PHY channels, especially when dealing with variable burst-to-burst latency protocols and pin-to-pin mapping issues.
Innovation Solution
A generic bit error rate analyzer system that includes a voltage translator and a programmable interface capable of communicating across multiple I/O standards, allowing for adaptable bit error rate determination across various high-speed serial standards, including USB 2.0, and capable of functioning both on-chip and off-chip, with a single analyzer circuit able to test multiple PHY interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate BER analyzer circuits are used for each PHY channel, then each channel can be tested independently, but the area overhead increases significantly for multiple PHY channels
Solution Approach 1:
The patent implements a single BER analyzer circuit that can be configured to test multiple different PHY channels through programmable interface configuration. The analyzer adapts its operation based on the selected PHY standard (e.g., USB 2.0, USB 3.0, SATA, SAS), allowing one circuit to perform the function of multiple dedicated circuits would otherwise be needed, thereby reducing area overhead while maintaining independent testing capability
Solution Approach 2:
The BER analyzer employs dynamic reconfiguration capability where the circuit's operational parameters, interface protocols, and testing methods can be changed on-the-fly to match different PHY standards. This dynamic adaptability allows the same hardware circuit to serve multiple channels with different requirements without requiring separate fixed-function circuits for each
2Adaptability or versatility
If off-chip BER analyzer is used, then comprehensive testing capability is achieved, but the cost becomes prohibitively high
Solution Approach 1:
The patent merges the BER analyzer functionality directly into the chip with the PHY interfaces, combining what were previously separate off-chip testing instruments into an integrated on-chip solution. This integration eliminates the need for expensive external testing equipment while maintaining comprehensive testing capability through the programmable interface that supports multiple PHY standards
3Measurement precision
If dedicated BER analyzers are implemented for each PHY standard, then accurate testing for each protocol is achieved, but the device complexity increases
Solution Approach 1:
The patent creates a universal BER analyzer that can accurately test multiple PHY standards (USB 2.0, USB 3.0, SATA, SAS, etc.) through a single circuit implementation. The analyzer uses programmable interface configuration to adapt its testing methodology to each specific protocol requirements, achieving protocol-specific accuracy without requiring separate dedicated circuits for each standard
4Adaptability or versatility
If off-chip BER analyzer is used, then variable burst-to-burst latency protocols can be tested, but loopback may not be feasible due to pin mapping issues
Solution Approach 1:
By integrating the BER analyzer on the same chip as the PHY interfaces, the patent enables direct internal loopback paths between transmit and receive channels without requiring external pin-to-pin mapping. This on-chip integration makes loopback testing feasible even when pin mappings don't align, while maintaining the ability to test variable burst-to-burst latency protocols through programmable interface configuration
Data Source
AI summary
Disclosed herein is a test apparatus for a device under test. The test apparatus includes a voltage translator coupled to receive test data from the device under test, over a physical interface, using one of a plurality of I/O standards, with the voltage translator being capable of communication using each of the plurality of I/O standards. A programmable interface is configured to receive the test data from the voltage translator. A bit error rate determination circuit is configured to receive the test data from the programmable interface and to determine a bit error rate of reception of the test data over the physical interface based upon a comparison of the test data to check data.