BER Reduction Buffer for Long High-Speed Serial Links
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Solution Overview
Problem
High-speed serial links face challenges in maintaining a low bit error rate (BER) at GHz speeds due to signal degradation over long distances, which can exceed the specified maximum BER, especially in applications like Fully Buffered DIMM systems, requiring a solution that improves BER without altering frequency requirements or electrical characteristics.
Innovation Solution
A bit error rate reduction buffer is introduced that operates on HSS links, capable of buffering data, checking for errors, and reducing skew between lanes, and can operate in both serial and parallel modes, physically dividing long HSS links into shorter segments and integrating a bit error rate reduction buffer to enhance signal quality and fault-isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If HSS links are extended to cover longer distances, then the coverage area is increased, but the bit error rate increases beyond specification limits
Solution Approach 1:
The patent divides a long HSS link into multiple shorter segments by inserting buffer devices at intermediate points. Each segment operates within acceptable signal degradation limits, and the buffer devices regenerate and retime signals to maintain low BER across the entire extended link length.
Solution Approach 2:
Buffer devices are introduced as intermediary components between transmitter and receiver in long HSS links. These buffers act as signal regeneration points that restore signal quality, effectively mediating the transmission over extended distances while maintaining specification compliance.
2Reliability
If buffer devices are added to reduce BER, then signal quality is improved, but device complexity increases
Solution Approach 1:
The buffer devices perform multiple functions simultaneously: they buffer data to reduce skew, retiming to synchronize signals, and regeneration to restore signal quality. This multi-functionality reduces the need for separate dedicated components for each function, thereby limiting the increase in overall device complexity.
3Stability of the object's composition
If data buffering is implemented to reduce skew, then timing synchronization is improved, but processing time increases
Solution Approach 1:
The buffer depth and operation are dynamically adjusted based on observed skew conditions and data flow patterns. This dynamic adaptation allows the system to achieve timing synchronization with minimal buffering delay, optimizing the trade-off between synchronization stability and time loss.
Data Source
AI summary
A disclosed example bit error rate reduction buffer comprises a data recovery circuit including differential bit pair inputs and differential bit pair outputs, a CRC circuit including differential bit pair inputs, differential bit pair outputs and a fault-isolation indicator, and a serializer including differential bit pair inputs and differential bit pair outputs. The differential bit pair outputs of the data recovery circuit being coupled to the differential bit pair inputs of the CRC circuit, the differential bit pair outputs of the CRC circuit being coupled to the differential bit pair inputs of the serializer, the differential bit pair inputs of the data recovery circuit to be driven by a first HSS link, the different bit pair outputs of the serializer to drive a second HSS link; and the fault-isolation indicator of the CRC circuit to indicate a fault when a fault is detected by the CRC circuit.