Bit Error Ratio Testing Confidence Exit Criterion

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Solution Overview

Problem

The margining operation in communication devices to determine optimal time/voltage slices for bit detection can be lengthy due to the need for testing each slice until a large number of bits are processed, which may not be necessary for slices with high confidence levels, leading to inefficient BER testing.

Innovation Solution

Implementing a confidence level-based exit criterion (CLi≧Y) to shorten the BER test duration for time/voltage slices, allowing the test to end when a sufficient accuracy level is reached, rather than requiring a fixed number of bits (Ni=X), thereby reducing the overall margining operation time.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a fixed number of bits (Ni=X) are processed for each time/voltage slice during BER testing, then measurement precision is improved, but loss of time increases

Engineering Contradiction:
ImproveBER estimate accuracyVSAvoidmargining operation duration
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies dynamics by transitioning from a static fixed-bit approach to a dynamic confidence-level-based exit criterion. The testing process adaptively adjusts the number of bits processed based on the calculated confidence level CLi for each time/voltage slice, allowing early termination when sufficient accuracy is achieved while maintaining rigorous testing when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter used to determine test termination from a fixed bit count Ni=X to a dynamic confidence level CLi. This parameter change allows the system to flexibly adjust testing duration based on the actual quality of the BER estimate, processing fewer bits when confidence is high and more bits when confidence is low, thereby resolving the contradiction between accuracy and time.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If BER testing is performed for all time/voltage slices with fixed bit processing, then reliability of BER estimates is improved, but productivity decreases

Engineering Contradiction:
ImproveBER estimate reliabilityVSAvoidmargining operation throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies partial action by processing only the necessary number of bits for each time/voltage slice based on its specific confidence level requirements. Instead of uniformly processing the maximum fixed number of bits for all slices, the system performs partial processing when high confidence is achieved early, maintaining reliability while improving overall productivity through optimized resource allocation.

Inventive Principle:
Principle #16Partial or excessive action

3Loss of time

If early termination of BER tests is implemented based on confidence levels, then loss of time is reduced, but measurement precision may deteriorate

Engineering Contradiction:
Improvetest durationVSAvoidBER estimate accuracy
Core Design Contradiction:
Loss of timeVSMeasurement precision

Solution Approach 1:

The patent implements feedback by continuously calculating the confidence level CLi during the BER testing process and using this feedback to dynamically adjust the testing duration. The confidence level serves as a real-time indicator of estimate quality, providing feedback that guides whether to continue or terminate testing, ensuring that early termination does not compromise precision below acceptable thresholds.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS9712263B1Bit error ratio tests
Publication Date: 2017.07.18 HEWLETT PACKARD ENTERPRISE DEV LP
  • US9712263B1 patent drawing
  • US9712263B1 patent drawing
  • US9712263B1 patent drawing

AI summary

An example communications device may include a slicer that may generate a digital output signal by thresholding a received signal according to variably set timing and voltage parameters. Testing circuitry may determine expected bit error ratios for multiple time-voltage slices by performing test operations corresponding respectively to the multiple time-voltage slices. Each of the test operations may include setting the timing and voltage parameters of the slicer based on the corresponding time-voltage slice, periodically measuring a bit error ratio based on the digital output signal and determining a confidence level for the measured bit error ratio, and in response to the determined confidence level equaling or exceeding a specified value, designating a current value of the measured bit-error ratio as the expected bit error ratio for the corresponding time-voltage slice and ending the test operation.