Semiconductor Integrated Circuit for Efficient BER Testing
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Solution Overview
Problem
Existing BER test methods for wireless communication apparatuses are inefficient and do not closely mimic actual operating conditions, particularly when measuring bit error rates, as they are constrained by standard-defined payload lengths and require lengthy test times.
Innovation Solution
A semiconductor integrated circuit configured to operate in both normal and test modes, featuring a demodulator, demodulated signal processing section, header analysis section, payload processing section, and control section, which allows for the reception of an unlimited number of payload bits and efficient BER measurement by disabling the demodulator upon test completion, thereby reducing test time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standard-defined payload lengths are used for BER testing, then test procedures are simplified, but test time increases and efficiency decreases
Solution Approach 1:
The payload processing section is configured to dynamically process payloads of arbitrary length rather than being constrained by fixed standard-defined lengths. The control section enables the payload processing section to handle test payloads of any length, allowing the system to adapt to different test requirements and reduce test time by processing only the necessary number of bits for BER measurement.
2Reliability
If conventional BER test methods are used, then testing is performed, but test efficiency is low and actual operating conditions are not closely mimicked
Solution Approach 1:
The system changes the payload length parameter from fixed standard-defined values to arbitrary lengths. By configuring the payload processing section to handle payloads of any length, the system can adjust the payload length parameter to match actual operating conditions more closely while maintaining measurement accuracy and improving test efficiency.
3Stability of the object's composition
If demodulator remains enabled during testing, then continuous operation is maintained, but test time is extended
Solution Approach 1:
The control section is configured to disable the demodulator in advance after completing the BER test measurement. This preliminary action of disabling the demodulator upon test completion allows the system to maintain operational continuity during normal operation while reducing overall test duration by stopping the demodulator once testing is finished.
Data Source
AI summary
A semiconductor integrated circuit, operable in a normal mode and a test mode, includes a demodulator, a demodulated signal processing section, a header analysis section, a payload processing section, and a control section. The demodulator demodulates a modulated wireless signal including a synchronization pattern, header, and payload, to generate a demodulated signal. The demodulated signal processing section detects the synchronization pattern from the demodulated signal, generates a synchronization detection signal synchronized to the synchronization pattern, and converts the demodulated signal into a received bit sequence. The header analysis section extracts and analyzes the header to obtain the number of bits of the payload. The payload processing section processes the payload. The control section disables the demodulator when processing of the number of bits in the payload is completed in the normal mode, and disables the demodulator synchronously with a signal indicating the end of a test in the test mode.