BERT Receiver Equalization and Stressed Eye Testing
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Solution Overview
Problem
Traditional testing methods for DDR4 memory systems, such as Rank Margining Test, do not support bit error rate (BER) testing and are unable to effectively evaluate the receiver's tolerance to timing and voltage stress, limiting their applicability to the higher speed requirements of DDR5 systems.
Innovation Solution
A system and method utilizing a bit error rate tester (BERT) with an electrical validation board and inter-symbol interference board to conduct receiver link equalization and BER testing, which includes loopback functionality and optional use of existing buses for signal transmission, eliminating the need for dedicated hardware and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods (Rank Margining Test) are used for DDR4 memory systems, then testing simplicity is maintained, but the ability to conduct BER testing and evaluate receiver tolerance to timing and voltage stress is lost
Solution Approach 1:
The testing system is designed to perform multiple functions including BER testing, receiver equalization testing, and stressed eye diagram acquisition using a unified architecture. The BERT can operate in different modes (loopback mode for BER testing, injection mode for stressed eye diagram) and the system can test multiple interfaces (DDR5 memory interface, SerDes interface) without requiring separate dedicated hardware systems for each function.
Solution Approach 2:
A calibration load board is introduced as an intermediary component between the BERT and the device under test. This calibration load board provides controlled impedance loading and signal routing capabilities, enabling the BERT to accurately generate and measure signals while maintaining system modularity. The calibration load board acts as a mediator that facilitates complex measurements without requiring direct modification of the device under test.
2Measurement precision
If dedicated hardware is designed for BER testing and receiver equalization testing, then testing accuracy is improved, but engineering costs and hardware complexity increase
Solution Approach 1:
The BERT is designed as a universal testing instrument that can perform BER testing, receiver equalization testing, stressed eye diagram acquisition, and loopback testing through software configuration rather than requiring separate dedicated hardware for each function. This multi-functionality maintains measurement precision across different test types while significantly reducing engineering costs by eliminating the need for multiple specialized hardware systems.
Solution Approach 2:
The system achieves different testing functions by changing operational parameters and configuration settings of the BERT rather than changing hardware components. For example, switching between loopback mode and injection mode, adjusting signal levels, and modifying test patterns are achieved through parameter changes that maintain hardware simplicity while providing comprehensive testing capabilities with high measurement precision.
3Adaptability or versatility
If new hardware is designed for DDR5 receiver testing, then testing capability is improved, but hardware costs and development time increase
Solution Approach 1:
The testing system is designed with universal interfaces and configurable functionality that can adapt to DDR5 memory interfaces, SerDes interfaces, and potentially future high-speed interfaces without requiring complete hardware redesign. The BERT can be configured through software to support different data rates, protocols, and test requirements, providing DDR5 testing capability while avoiding the complexity of dedicated hardware development for each interface standard.
Solution Approach 2:
The system employs dynamic reconfiguration capabilities where the BERT can switch between different operating modes (loopback mode, injection mode), adjust signal parameters (data rate, voltage levels, timing), and adapt test patterns based on the specific testing requirements. This dynamic adaptability enables comprehensive DDR5 receiver testing without requiring static dedicated hardware for each test scenario, reducing overall hardware development complexity.
Data Source
AI summary
A method of conducting bit error rate testing of an electronic device under test using a bit error rate tester (BERT) includes configuring the BERT with one or more of jitter, noise, and timing settings to derive a desired receiver stressed eye diagram; connecting the electronic device under test to the BERT via an inter-symbol interference channel that introduces delays for creation of the desired receiver stressed eye diagram at the electronic device under test; the BERT placing the electronic device under test into a loopback mode whereby data transmitted to the electronic device under test by the BERT is transmitted back to the BERT for comparison to the data transmitted to the electronic device under test; the BERT transmitting a data pattern into the electronic device under test; and the BERT comparing the data pattern transmitted to the electronic device under test by the BERT to data received back from the electronic device under test during the loopback mode to detect a bit error rate.