Between-fin floating-gate memory for logic integration
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Solution Overview
Problem
Integrating conventional flash memory with logic circuitry on a chip increases production costs and can negatively impact logic transistor performance due to additional processing steps required.
Innovation Solution
The implementation of semi-volatile embedded memory with between-fin floating-gate devices, which includes forming fin structures on a semiconductor substrate, depositing an oxide layer between them, and creating floating gates between these structures to enhance memory performance while minimizing additional processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional flash memory is integrated with logic circuitry on the same chip, then memory integration is achieved, but production cost increases significantly and logic transistor performance deteriorates due to additional processing steps
Solution Approach 1:
The patent merges memory and logic circuitry fabrication into a single unified process flow. The between-fin floating-gate memory structure is formed using the same fin formation, oxide deposition, and polysilicon gating steps as the logic transistors, eliminating the need for separate memory fabrication processes and reducing production costs while achieving memory integration on the same chip
2Adaptability or versatility
If conventional flash memory is integrated with logic circuitry on the same chip, then memory integration is achieved, but logic transistor performance deteriorates due to additional processing steps
Solution Approach 1:
The patent combines memory and logic fabrication processes so that both structure types are formed simultaneously using identical processing steps. This merging approach ensures that logic transistors are not exposed to additional or different processing conditions that could degrade their performance, while still achieving memory integration on the same chip
3Speed
If between-fin floating-gate memory structures are formed, then write speed and retention time are improved, but device complexity increases
Solution Approach 1:
The patent transitions from planar memory structures to three-dimensional between-fin floating-gate structures. By utilizing the vertical dimension and positioning floating gates between adjacent fins, the structure achieves improved write speed and retention time while the fabrication complexity remains comparable to standard FinFET logic transistor manufacturing
Data Source
AI summary
Embodiments of the present disclosure provide techniques and configurations for semi-volatile embedded memory with between-fin floating gates. In one embodiment, an apparatus includes a semiconductor substrate and a floating-gate memory structure formed on the semiconductor substrate including a bitcell having first, second, and third fin structures extending from the substrate, an oxide layer disposed between the first and second fin structures and between the second and third fin structures, a gate of a first transistor disposed on the oxide layer and coupled with and extending over a top of the first fin structure, and a floating gate of a second transistor disposed on the oxide layer between the second and third fin structures. Other embodiments may be described and/or claimed.