Bevel Plasma Blocking Layer for Silicidation Contamination

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Solution Overview

Problem

The formation of a metal silicide layer in the wafer bevel region during the silicidation process leads to contamination of the etching machine and reduces the reliability and yield of semiconductor fabrication processes.

Innovation Solution

A blocking layer, such as a silicon dioxide layer, is formed only in the wafer bevel region using bevel plasma treatment before the metal silicidation process, preventing the formation of a metal silicide layer in this region and thereby avoiding contamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a metal silicide layer is formed during the silicidation process, then contact resistance is reduced, but contamination occurs in the etching machine chamber

Engineering Contradiction:
Improvecontact resistanceVSAvoidcontamination
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies local quality by forming a blocking layer selectively only in the wafer bevel region, while leaving the active device regions uncovered. This localized approach prevents metal silicide formation only where it causes contamination (bevel region), while allowing it in regions where it provides benefit (contact regions), thus resolving the contradiction between reducing contact resistance and preventing contamination

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The blocking layer acts as an intermediary substance that prevents direct contact between the metal layer and the silicon surface in the bevel region. This intermediary layer blocks the formation of metal silicide in the bevel region while allowing the silicidation process to proceed normally in the active regions, thereby preventing contamination without affecting contact resistance

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If a blocking layer is formed in the wafer bevel region, then contamination is prevented, but process complexity increases

Engineering Contradiction:
ImprovecontaminationVSAvoidprocess complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The blocking layer is formed in advance before the metal silicide formation process, specifically targeting the wafer bevel region. This preliminary action prevents the need for complex contamination removal procedures later, and the blocking layer formation integrates smoothly into the existing process flow, adding minimal complexity while effectively preventing contamination

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes in the plasma treatment process (such as gas composition, power, and time) to achieve selective blocking layer formation only in the bevel region. By optimizing these parameters, the process achieves the desired selectivity without requiring additional process steps, thereby minimizing the increase in process complexity

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively prevents metal silicide layer formation in the wafer bevel region, improving the reliability and yield of the semiconductor fabrication process by reducing contamination in the etching machine.

Implementation Method 1

a bevel plasma treatment is performed on the semiconductor wafer to form a blocking layer only in the wafer bevel region

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

a bevel plasma treatment is performed on the semiconductor wafer to form a blocking layer only in the wafer bevel region

Methodology Applied
Scientific EffectPlasma: Plasma

Data Source

PatentUS10658173B2Method for fabricating a semiconductor structure on a semiconductor wafer
Publication Date: 2020.05.19 UNITED MICROELECTRONICS CORP
  • US10658173B2 patent drawing
  • US10658173B2 patent drawing
  • US10658173B2 patent drawing

AI summary

A method for fabricating a semiconductor structure on a semiconductor wafer is disclosed. A semiconductor wafer having a first region, a second region, and a wafer bevel region is provided. The wafer bevel region has a silicon surface. A first semiconductor structure is formed in the first region and a second semiconductor structure is formed in the second region. The semiconductor wafer is subjected to a bevel plasma treatment to form a blocking layer only in the wafer bevel region. A silicidation process is then performed to form a silicide layer only in the first region and the second region.