Decoupling Capacitor Placement Between BGA Balls

The patent transitions the capacitor placement from traditional PCB or package-level locations to the bump-to-bump dimension within the IC package itself. By placing capacitors between adjacent bumps (e.g., between first and second bumps), the solution operates at a finer spatial dimension, reducing the current loop area and thus loop inductance, while improving power distribution efficiency at the bump level.

The patent applies local quality by placing decoupling capacitors specifically at strategic bump locations within the package rather than using a uniform PCB-level approach. Each capacitor is positioned between specific bumps (e.g., between first and second bumps, or between third and fourth bumps) to locally address power distribution needs and minimize local loop inductance, rather than applying a general solution across the entire system.

The patent merges the decoupling capacitor function with the existing bump structure and package substrate. Instead of adding separate PCB-mounted capacitors or package-level decoupling components, the solution integrates capacitors directly into the bump interconnection architecture, utilizing the same physical space and structural elements already present in the package, thereby reducing overall system cost while maintaining power delivery reliability.

The patent extracts the decoupling function from traditional external components (PCB capacitors, package-level decoupling capacitors) and relocates it to the bump level within the package. This extraction allows the use of smaller, more efficient capacitors that are integrated into the existing bump structure, eliminating the need for separate, more expensive external decoupling components while maintaining or improving power delivery reliability.

The patent applies preliminary action by pre-defining specific capacitor placement locations between bumps during the package design phase. The capacitor positions are predetermined (e.g., between first and second bumps, or between third and fourth bumps) based on the bump pitch and package geometry, allowing manufacturing processes to follow established guidelines rather than requiring complex real-time positioning, thus reducing the actual manufacturing precision burden while maximizing space utilization.

The patent segments the package into distinct bump groups with capacitors placed between specific segments (e.g., between first and second bumps, between third and fourth bumps). This segmentation approach allows each capacitor to be positioned independently at standardized intervals, simplifying the manufacturing process by creating repeatable placement patterns rather than requiring continuous precision positioning across the entire package surface.