BGA Pad Layout for Characteristic Impedance in Component Packages
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Solution Overview
Problem
Existing electronic component packages face challenges in maintaining characteristic impedance when BGA pads are densely disposed, leading to reduced signal transmission efficiency and increased size constraints.
Innovation Solution
The electronic component package design includes signal and ground electrode pads with reduced suppression widths and adjusted intervals to maintain impedance matching, even with densely packed pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If BGA pads are densely disposed to reduce size, then the device size is reduced, but the characteristic impedance of the transmission path deteriorates
Solution Approach 1:
The patent applies local quality by differentiating the suppression width of solder resist or ceramic coat based on pad function. Signal electrode pads have a first suppression width while ground electrode pads have a second suppression width that is smaller than the first. This local differentiation maintains appropriate gap distances between signal and ground pads, preserving characteristic impedance while enabling dense pad disposal for size reduction.
2Reliability
If the suppression width of solder resist or ceramic coat is reduced to maintain gap distance, then the characteristic impedance is maintained, but the pad strength is reduced
Solution Approach 1:
The patent applies local quality by differentiating the suppression width of solder resist or ceramic coat based on pad function. Signal electrode pads have a first suppression width while ground electrode pads have a second suppression width that is smaller than the first. This local differentiation maintains appropriate gap distances between signal and ground pads, preserving characteristic impedance while enabling dense pad disposal for size reduction.
Data Source
AI summary
An electronic component package in which pads are disposed on an x-y plane in a lattice pattern in an x-direction and a y-direction orthogonal to the x-direction at a predetermined pitch, in which a suppression width of a solder resist or a ceramic coat and a size of a pad of a signal electrode pad disposed on the outermost periphery and configured to input or output a high-frequency signal, and a ground electrode pad adjacent to the signal electrode pad in the x-direction and the y-direction are formed to be smaller than a suppression width of the solder resist or the ceramic coat of other pads and a size of a pad.


