BGA Package Plating Traces Under Chip
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Solution Overview
Problem
The challenge in ball grid array (BGA) packages is to increase the number of signal I/O terminals while maintaining a small package size and reducing costs, as the traditional approach of adding metal layers is costly and limits the number of routing traces, making it difficult to accommodate additional lands and connections.
Innovation Solution
The solution involves strategically interrupting the periodicity of the land array at the substrate edge to place additional plating traces leading towards the interior, allowing for more signal lands and traces under the chip, which are then connected to the plating bar, enabling the use of existing sites for additional signal vias and solder balls without adding metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If additional metal layers are added to increase the number of routing traces, then the number of signal I/O terminals increases, but the manufacturing cost increases significantly
Solution Approach 1:
The patent utilizes the third dimension (vertical space under the chip) to place additional lands and traces. By routing traces underneath the chip area and using the substrate thickness to accommodate via structures, the design effectively adds routing capacity without adding horizontal metal layers, thereby avoiding the cost increase associated with additional plating layers.
Solution Approach 2:
The patent segments the routing paths by creating separate trace regions: peripheral traces for power/ground connections and central traces under the chip for signal connections. This segmentation allows independent optimization of each trace group and enables the use of the previously underutilized central substrate area for additional signal routing.
2Area of stationary object
If the package size is reduced to maintain small form factor, then the area available for routing traces decreases, but the number of signal I/O terminals needs to increase
Solution Approach 1:
The patent transitions from two-dimensional peripheral routing to three-dimensional routing by utilizing the vertical space and the area under the chip. Traces are routed through the substrate thickness via vias, and additional lands are placed in the central region under the chip, effectively adding routing capacity without increasing the planar package footprint.
Solution Approach 2:
The patent merges the functions of peripheral and central substrate regions by utilizing both areas for routing. The central region, traditionally left empty or used only for mechanical support, is combined with the peripheral region to provide additional routing paths, thereby increasing the number of available signal I/O terminals within the same package area.
3Quantity of substance
If more routing traces are added to accommodate additional lands, then the number of signal I/O terminals increases, but the trace pitch decreases making manufacturing more difficult
Solution Approach 1:
The patent applies different trace pitch requirements to different regions: the peripheral region maintains larger trace pitch for power/ground connections, while the central region under the chip utilizes optimized trace pitch for signal connections. This local quality approach allows the manufacturing process to handle different pitch requirements in different areas, reducing the overall difficulty compared to uniformly small pitch across the entire package.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the number of signal terminals by up to 290% in a 12×12 mm BGA package, allowing for scalable reductions in trace pitch, thereby retaining cost advantages and enhancing connectivity without increasing metal layer costs.
Implementation Method 1
the most economical deposition technique is electroplating. This method requires routing traces, which connect the bump pads and the vias to the plating bars for supplying the plating current.
Data Source
AI summary
A semiconductor flip-chip ball grid array package (600) with one-metal-layered substrate. The sites (611) of a two-dimensional array become usable for attaching solder balls of the signal (non-common net assignment) I/O type to the substrate under the chip area (601), when the sites can be routed for metal plating (620). The space to place a maximum number (614) of signal routing traces is opened up by interrupting the periodicity of the site array from the edge (602) of the substrate towards the center under the chip. The periodicity is preferably interrupted by depopulating entire aligned lines and rows of the two-dimensional array.