Opposite-Side BGA SoC Memory Package Thermal Separation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current package-on-package (PoP) technology is limited by minimum thickness and lacks thermal separation between the System on a Chip (SoC) and memory die, leading to thermal coupling issues that slow down both components and restrict advancements in reducing z-height and improving thermal properties.
Innovation Solution
A semiconductor package design where the SoC and memory die are coupled to opposite sides of a ball grid array (BGA) substrate, thermally separating them, with a voltage regulator and heat sink material positioned to reduce overall height and enhance thermal management, allowing for improved power delivery and signal integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If memory die are stacked near the SoC in PoP packages to reduce z-height, then package thickness is reduced, but thermal separation between SoC and memory die is lost causing thermal coupling and performance throttling
Solution Approach 1:
The patent segments the package structure by placing memory die and SoC on opposite sides of the BGA substrate rather than stacking them vertically. This spatial segmentation maintains thermal separation while achieving reduced z-height through the flat package profile.
Solution Approach 2:
The patent transitions from vertical stacking (z-dimension) to horizontal placement on opposite substrate surfaces (x-y plane). This dimensional change allows thermal separation to be maintained while achieving thin package thickness through the substrate's flat profile.
2Productivity
If memory die are thermally coupled to SoC in PoP packages, then integration density is improved, but heat generated from SoC heats the memory die causing throttling
Solution Approach 1:
The patent extracts the memory die from the vertical stack near the SoC and relocates them to the opposite side of the BGA substrate. This extraction eliminates the thermal coupling pathway while maintaining integration through the substrate's interconnect structure.
Solution Approach 2:
The BGA substrate acts as a thermal intermediary that physically separates the SoC and memory die while providing electrical interconnection. This intermediary structure enables integration density without direct thermal coupling between the heat-generating SoC and the memory die.
3Length of moving object
If z-height in PoP packages is reduced to achieve thinner packages, then package thickness is decreased, but thermal density between SoC and memory die increases causing performance degradation
Solution Approach 1:
The patent segments the thermal pathways by placing heat-generating components on opposite sides of the substrate, preventing thermal concentration. This segmentation allows thin package design without the thermal density problems that arise from vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves reduced z-height, increased thermal separation, and enhanced performance by allowing the memory die to operate at faster speeds and the SoC to maintain performance without throttling, while also reducing the overall package height and thermal density.
Implementation Method 1
Coupling the processor die and the memory die on opposite sides of the BGA substrate thermally separates the die
Data Source
AI summary
A semiconductor package includes a processor die (e.g., an SoC) and one or more memory die (e.g., DRAM) coupled to a ball grid array (BGA) substrate. The processor die and the memory die are coupled to opposite sides of the BGA substrate using terminals (e.g., solder balls). The package may be coupled to a printed circuit board (PCB) using one or more terminals positioned around the perimeter of the processor die. The PCB may include a recess with at least part of the processor die being positioned in the recess. Positioning at least part of the processor die in the recess reduces the overall height of the semiconductor package assembly. A voltage regulator may also be coupled to the BGA substrate on the same side as the processor die with at least part of the voltage regulator being positioned in the recess a few millimeters from the processor die.