Ball Grid Array Layout With Split Pitch for Via Space and Pin Density
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional ball grid arrays face poor solder ball utilization in the inner row region due to the need for space for vias, which limits the number of input/output pins and results in insufficient space for vias on printed circuit boards when trying to increase pin density.
Innovation Solution
The solution involves arranging solder balls in the inner row region with a larger ball pitch to optimize space utilization for vias, while the outer row region uses a smaller ball pitch to increase pin density, allowing for a higher number of pins without compromising via space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a smaller ball pitch is used to increase the quantity of input/output pins, then the pin density increases, but the printed circuit board does not have enough space for vias in the inner row region
Solution Approach 1:
The patent applies different ball pitches to different regions of the ball grid array. The inner row region uses a first ball pitch that is determined according to the minimum trace width relative to via size, ensuring sufficient space for vias. The outer row region uses a second ball pitch that is smaller than the first ball pitch, maximizing pin density where via space is not constrained. This regional differentiation resolves the contradiction by optimizing each area for its specific functional requirements.
2Quantity of substance
If a smaller ball pitch is used to increase the quantity of input/output pins, then the pin density increases, but the solder ball utilization rate in the inner row region decreases
Solution Approach 1:
The patent implements local quality optimization by assigning different ball pitch values to different regions. In the inner row region, a larger first ball pitch is used to maintain high solder ball utilization rate and ensure proper via spacing. In the outer row region, a smaller second ball pitch is used to increase overall pin quantity. This regional strategy ensures that solder balls are utilized efficiently where needed while still achieving high total pin count.
Data Source
AI summary
A ball grid array and a configuration method of the same are provided. The ball grid array is formed on a printed circuit board and includes an inner row region and an outer row region. The inner row region includes a plurality of first solder balls that are arranged by a first ball pitch. The first solder balls respectively correspond to a plurality of predetermined vias, and the first ball pitch is determined according to a minimum trace width that is relative to a via size of the predetermined vias. The outer row region surrounds the inner row region and includes a plurality of second solder balls that are arranged by a second ball pitch. The second ball pitch is smaller than the first ball pitch.