BGA STIM Package Architecture With Low-Temp Solder Reflow
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Solution Overview
Problem
The existing temperature hierarchy in ball grid array (BGA) solder thermal interface material (STIM) packages causes the STIM to melt and create voids during reflow processes, leading to inferior thermal performance and increased thermal resistance.
Innovation Solution
The use of a low-temperature solder (LTS) paste with a melting point less than that of the STIM, composed of alloys like Sn and Bi, which prevents melting and void formation by establishing a controlled temperature hierarchy, allowing for the implementation of indium STIMs on BGA packages without compromising thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If STIM is used in BGA packages, then thermal performance is improved, but STIM melts and creates voids during reflow processes
Solution Approach 1:
The patent changes the melting point parameter of the solder paste by using a low-temperature solder (LTS) formulation with a melting point below that of the STIM material. This parameter change ensures that during the BGA reflow process, the LTS paste melts and reflows at a temperature that does not cause the STIM to melt, thereby preventing void formation while maintaining the thermal performance benefits of STIM.
2Ease of manufacture
If conventional solder paste is used, then BGA reflow is achieved, but STIM melts and creates voids increasing thermal resistance
Solution Approach 1:
The patent modifies the temperature parameter of the reflow process by implementing a controlled temperature hierarchy where the LTS paste melting point is deliberately set below the STIM melting point. This allows the BGA reflow process to proceed effectively while preventing STIM degradation, thereby achieving both ease of manufacture and low thermal resistance.
Solution Approach 2:
The LTS paste acts as an intermediary material between the BGA package and the STIM. By introducing this intermediate layer with specific thermal and mechanical properties, the patent enables the BGA reflow process to occur without directly exposing the STIM to temperatures that would cause melting and void formation, thus maintaining manufacturing precision.
3Stability of the object's composition
If different TIMs are used for BGA IHS packages, then void formation is prevented, but thermal properties become inferior
Solution Approach 1:
The patent changes the key parameter of the TIM system by using STIM material with a melting point higher than the LTS paste melting point. This parameter relationship reversal allows the package to use superior thermal conductivity materials (STIM) while preventing the melting issue through the controlled temperature hierarchy established by the LTS paste.
Solution Approach 2:
The LTS paste serves as a protective intermediary that decouples the reflow process temperature from the STIM melting point. This intermediary layer absorbs the thermal stress during reflow, allowing the STIM to maintain its superior thermal properties without undergoing phase change or creating voids.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables improved thermal performance and reliability of BGA packages by preventing STIM melting during reflow processes, maintaining thermal efficiency, and reducing thermal resistance.
Implementation Method 1
The LTS paste has a melting point that is less than a melting point of the STIM
Implementation Method 2
a solder thermal interface material (STIM) coupling a top surface of the die to the bottom surface of the IHS
Data Source
AI summary
Embodiments include semiconductor packages and methods of forming such packages. A semiconductor package includes a die on a package substrate, an integrated heat spreader (IHS) on the package substrate and above the die, and a solder thermal interface material (STIM) coupling the die to the IHS. The semiconductor package includes a low-temperature solder (LTS) paste comprising an alloy of tin and bismuth (Bi), and the LTS paste on a bottom surface of the package substrate having a ball grid array. The LTS paste may have a weight percentage of Bi greater than 35% and a melting point less than or equal to a melting point of the STIM, where the STIM includes indium. The weight percentage of Bi may be between approximately 35% to 58%. The semiconductor package may include a solder ball coupling the LTS paste on the package substrate to the LTS paste on a second package substrate.


