BGA Substrate with Integrated Passive Device Chip Scale Module
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Solution Overview
Problem
Current semiconductor packages with stacked dies lack flexibility in incorporating subcomponents like integrated circuits and integrated passive devices, limiting their functionality, performance, and increasing costs while maintaining a smaller footprint.
Innovation Solution
The method involves using a ball grid array substrate with integrated metal layers, applying a thermal conductive adhesive, and forming interconnects to integrate a known good chip scale module package, which includes semiconductor dies with IPDs or ICs, allowing for increased functionality and connectivity through various configurations such as LGA or BGA, and optionally using a thermally-enhanced substrate with a cavity for enhanced thermal performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a stacked-die arrangement is used to reduce package size, then the package footprint is reduced, but the flexibility to incorporate subcomponents such as IPDs and ICs is limited
Solution Approach 1:
The patent implements a nested structure where chip scale module packages (CSMPs) containing IPDs are placed within the BGA package footprint. The CSMPs are positioned in the spaces between the stacked dies and the package substrate, effectively nesting additional functionality within the existing compact structure without increasing the overall package footprint.
Solution Approach 2:
The patent utilizes the vertical dimension and lateral spaces within the package by implementing multiple stacking levels and positioning CSMPs in available spaces. This multi-level arrangement allows incorporation of IPDs and ICs in three-dimensional space rather than being constrained to a single plane, thereby increasing versatility without expanding the two-dimensional footprint.
2Adaptability or versatility
If multiple separate semiconductor packages are used to provide diverse functionality, then the flexibility and functionality are increased, but the package size and cost increase
Solution Approach 1:
The patent merges multiple functional components into a single integrated BGA package. Multiple CSMPs containing different IPDs (resistors, capacitors, inductors, filters, BALUNs) and ICs are combined with stacked dies within one package substrate, providing diverse functionality that would otherwise require multiple separate packages while maintaining a compact footprint.
Solution Approach 2:
The BGA package substrate is designed as a universal platform that can accommodate various types of components including stacked dies, CSMPs with IPDs, and ICs. This multi-functional substrate design allows a single package to perform multiple functions that would traditionally require separate specialized packages.
3Ease of manufacture
If traditional wire-bonding is used to connect stacked dies, then the manufacturing process is simple, but the circuit density and performance are limited
Solution Approach 1:
The patent replaces traditional wire-bonding mechanical connection methods with bump bonding technology. Bump bonds provide direct electrical and mechanical contact between dies and substrate, eliminating the need for wire loops and bonds. This substitution increases circuit density by reducing the space required for interconnections while maintaining manufacturing feasibility through automated bump bonding processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher performance, lower cost, and smaller size semiconductor packages with enhanced functionality by integrating IPDs and ICs within the package, promoting increased circuit density and thermal management, suitable for applications like WLAN, Bluetooth, and digital signal processing.
Implementation Method 1
applying a thermal conductive adhesive over a first surface of the BGA substrate
Data Source
AI summary
A semiconductor package includes a ball grid array (BGA) substrate having integrated metal layer circuitry, a flip chip chip scale module package (CSMP) having a first integrated passive device (IPD), the flip chip chip scale module package attached to the BGA substrate, and an application die attached to the IPD. A method of manufacturing a semiconductor package includes providing a BGA substrate having integrated metal layer circuitry, attaching a flip chip CSMP having a first IPD to the BGA substrate, and attaching an application die to the IPD.


