Bottom Gate Bottom Contact Transistor Two-Step Etching

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Transistors with oxide semiconductors face challenges in maintaining high reliability and stable threshold voltage shift during long-term usage, particularly in bias-temperature stress tests, due to variations in semiconductor layer thickness and etching processes.

Innovation Solution

A two-step etching method is employed, using gases with different chlorine and fluorine compositions to selectively etch conductive films, ensuring the semiconductor layer thickness remains consistent, thereby reducing off-state current and maintaining high on-state current while preventing the underlying layer from thinning.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single-step etching method is used to process conductive films, then the manufacturing process is simple and fast, but the semiconductor layer thickness varies and the underlying layer thins, reducing reliability

Engineering Contradiction:
Improveetching process speedVSAvoidsemiconductor layer thickness consistency
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The etching process is divided into two distinct steps: a first etching step that removes the upper conductive film layer, and a second etching step that selectively removes the lower conductive film layer while protecting the semiconductor layer. This segmentation allows each step to be optimized for its specific purpose, achieving both high productivity and precise thickness control.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A protective film is formed over the semiconductor layer before the etching process begins. This preliminary protective action prevents the semiconductor layer from being etched during the first etching step, ensuring thickness consistency while maintaining process efficiency.

Inventive Principle:
Principle #10Preliminary action

2Loss of time

If high electric field intensity is applied during GBT test to accelerate reliability testing, then the test duration is shortened, but the threshold voltage shifts significantly, indicating reduced reliability

Engineering Contradiction:
Improvereliability test durationVSAvoidthreshold voltage stability
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

The protective film is designed as a temporary, disposable element that is present only during the etching process. After etching completion, the protective film is removed, leaving no residual impact on the semiconductor device. This allows aggressive etching conditions to be used without permanently affecting the semiconductor layer or device reliability.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in transistors with improved reliability and stable switching characteristics, as evidenced by minimal threshold voltage shift during bias-temperature stress tests, and reduced variation in semiconductor layer thickness, enhancing overall device performance.

Implementation Method 1

an etching method including at least a first etching step and a second etching step. In the first etching step, a method in which etching rates for at least a second film and a third film are high is employed

Methodology Applied
Scientific EffectEtching:

Implementation Method 2

an etching method in which the etching rate for the first film is higher than that in the first etching step and the etching rate for a layer provided below and in contact with the first film is lower than that in the first etching step is employed in the second etching step

Methodology Applied
Scientific EffectChemical Vapour Deposition: Chemical Vapour Deposition

Data Source

PatentUS9837513B2Semiconductor device and manufacturing method thereof
Publication Date: 2017.12.05 SEMICON ENERGY LAB CO LTD
  • US9837513B2 patent drawing
  • US9837513B2 patent drawing
  • US9837513B2 patent drawing

AI summary

When a transistor having bottom gate bottom contact structure is manufactured, for example, a conductive layer constituting a source and a drain has a three-layer structure and two-step etching is performed. In the first etching process, an etching method in which the etching rates for at least the second film and the third film are high is employed, and the first etching process is performed until at least the first film is exposed. In the second etching process, an etching method in which the etching rate for the first film is higher than that in the first etching process and the etching rate for a “layer provided below and in contact with the first film” is lower than that in the first etching process is employed. The side wall of the second film is slightly etched when a resist mask is removed after the second etching process.