Bi-Gate Thin Film Transistor Reducing Shielding Effect
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Solution Overview
Problem
Current coplanar thin film transistors (TFTs) experience reduced carrier mobility due to a shielding effect caused by the source/drain layers, which obstructs the electrical field and prevents charge accumulation, leading to increased impedance in the carrier transmission channel.
Innovation Solution
A TFT design featuring a bi-gate structure where the first gate layer induces a carrier transmission channel between the source/drain layers, and the second gate layer, connected through a via to maintain the same voltage level, reduces the shielding effect by overlapping with the carrier transmission channel to enhance carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a coplanar TFT structure is used, then the manufacturing process is simplified, but the source/drain layer shields the electrical field from the gate layer, reducing carrier mobility
Solution Approach 1:
The patent introduces a second gate layer above the passivation layer, creating a vertical stacking configuration. This dimensional change allows the gate structure to extend in the vertical direction, enabling the gate electrode to be positioned above the source/drain layers rather than adjacent to them, thereby eliminating the shielding effect while maintaining coplanar manufacturing advantages
Solution Approach 2:
The patent implements a stacked configuration where the first gate layer is nested below the source/drain layers and the second gate layer is nested above the passivation layer. This nesting arrangement allows both gate layers to function simultaneously without spatial interference, with the lower gate layer controlling the channel and the upper gate layer compensating for the shielding effect
2Ease of manufacture
If the gate layer is positioned below the source/drain layer, then the TFT structure is easier to manufacture, but the electrical field is shielded and charge accumulation is prevented
Solution Approach 1:
By adding the second gate layer in the vertical dimension above the passivation layer, the patent creates a three-dimensional gate structure that projects over the source/drain regions. This vertical extension allows the electrical field to penetrate through the source/drain layers and accumulate charges in the channel region, overcoming the shielding effect inherent in planar configurations
Solution Approach 2:
The patent combines the functions of two gate layers working in unison - the first gate layer provides the primary gate control from below, while the second gate layer provides additional field penetration from above. This merging of dual gate structures creates a synergistic effect that enhances charge accumulation capability while maintaining manufacturing simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-gate structure effectively reduces the shielding effect, improving carrier mobility by ensuring the first and second gate layers maintain a consistent voltage level, thereby optimizing carrier transmission and reducing impedance.
Implementation Method 1
the first gate layer induces a first carrier transmission channel at the semiconductor layer
Implementation Method 2
the second gate layer induces a second carrier transmission channel at the semiconductor layer
Data Source
AI summary
A thin film transistor (TFT) is provided, which includes a substrate, a first gate layer, an insulation layer, a first source/drain layer, a second source/drain layer, a semiconductor layer, a passivation layer and a second gate layer. The first gate layer is disposed on the substrate. The insulation layer is disposed on the first gate layer. The first source/drain layer is disposed on the insulation layer. The second source/drain layer is disposed on the insulation layer. The semiconductor layer is disposed on the insulation layer and covers the first source/drain layer and the second source/drain layer. The passivation layer is disposed on the insulation layer and covers the semiconductor layer. The second gate layer is disposed on the passivation layer and contacts the first gate layer through a via so that the two gate layers keep a same voltage level.