Bi-layer Dielectric Cap for Copper Interconnect Reliability
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Solution Overview
Problem
In semiconductor devices, particularly for copper interconnects with narrow pitches, Time-Dependent Dielectric Breakdown (TDDB) and micro-trenching issues due to misalignment between lines and vias lead to performance degradation, as the interface between the cap dielectric and low-k dielectric materials facilitates copper diffusion and metal residue formation.
Innovation Solution
The implementation of a bi-layer dielectric cap structure between copper interconnect lines, formed through a process involving cavity creation, barrier and liner deposition, metal filling, planarization, and selective cap deposition, which addresses copper diffusion and metal residue issues while preventing micro-trenching by creating a recessed space between lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If copper interconnects are used to reduce propagation delays and power consumption, then performance is improved, but copper diffusion and metal residue formation occur at the interface between cap dielectric and low-k dielectric materials
Solution Approach 1:
The patent introduces a cap dielectric layer as an intermediary barrier between the copper interconnect and the low-k dielectric material. This cap dielectric prevents direct contact between copper and low-k dielectric, thereby blocking copper diffusion and preventing metal residue formation at the interface, which resolves the harmful effects while maintaining the performance benefits of copper interconnects
Solution Approach 2:
The patent employs a composite dielectric structure consisting of a cap dielectric layer combined with low-k dielectric material. This composite structure leverages the diffusion-blocking properties of the cap dielectric while maintaining the low capacitance characteristics of the low-k material, achieving both reliability improvement and performance optimization
2Use of energy by moving object
If narrow pitch interconnects are implemented to reduce power consumption, then energy efficiency is improved, but misalignment between lines and vias causes micro-trenching issues
Solution Approach 1:
The patent applies beforehand cushioning by forming the cap dielectric layer in advance before subsequent processing steps. This pre-formed cap dielectric provides a protective cushion that prevents micro-trenching from occurring during via formation and etching processes, compensating for potential misalignment issues that may arise in narrow pitch interconnects
3Device complexity
If a single dielectric cap is used to prevent copper diffusion, then the structure is simple, but TDDB performance degradation occurs due to the interface between cap dielectric and low-k dielectric
Solution Approach 1:
The patent segments the dielectric cap into multiple functional layers: a cap dielectric layer for diffusion protection and a low-k dielectric layer for capacitance reduction. This segmentation allows each layer to perform its specific function optimally, preventing TDDB performance degradation while maintaining structural simplicity through clear functional division
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances TDDB performance and prevents voltage breakdown degradation by reducing copper diffusion and eliminating metal residues, thereby improving the reliability and efficiency of copper interconnects in semiconductor devices.
Implementation Method 1
the interface between the cap dielectric and low-k dielectric materials facilitates copper diffusion
Implementation Method 2
a barrier material is deposited over a first exposed surfaces of each cut cavity of the plurality of cut cavities to form a barrier in each cut cavity
Implementation Method 3
a liner material is deposited over a second exposed surfaces of the barrier material
Data Source
AI summary
A copper interconnect with an embedded dielectric cap between lines comprises a plurality of interconnect lines formed in a dielectric layer of a semiconductor device. The copper interconnect further comprises a first dielectric cap formed between each interconnect line of the plurality of interconnect lines. The copper interconnect further comprises a second dielectric cap formed on top of the plurality of interconnect lines and the first dielectric cap, wherein the second dielectric cap formed on top of the first dielectric cap forms a bi-layer dielectric cap between the plurality of interconnect lines.