Bi-layer Dislocations in Semiconductor Channel Stress Engineering

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Solution Overview

Problem

Existing methods for forming stressor regions in semiconductor devices, such as MOSFETs, are not entirely satisfactory in enhancing carrier mobility and device performance, particularly in scaled-down semiconductor integrated circuits.

Innovation Solution

A method involving a series of pre-amorphous implantation and annealing processes with stress film deposition and removal is employed to form bi-layer dislocations in the source and drain regions, which provides consistent stress within the channel region and improves carrier mobility without significant cost additions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing methods for forming stressor regions are used, then device fabrication can proceed with standard processes, but carrier mobility and device performance are not sufficiently enhanced

Engineering Contradiction:
Improvedevice performanceVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The stressor region formation is divided into multiple discrete steps: depositing a stress film over the semiconductor structure, performing pre-amorphous implantation to create dislocations, and selectively removing portions of the stress film. This segmentation allows each step to be optimized independently while maintaining overall process compatibility with existing manufacturing workflows

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Pre-amorphous implantation is performed as a preliminary action before final stressor region formation. This implantation creates controlled dislocations in the semiconductor lattice that serve as nucleation sites for subsequent stress-induced crystallization, enabling more effective stressor region formation without requiring complete process retooling

Inventive Principle:
Principle #10Preliminary action

2Productivity

If geometry size is scaled down to increase functional density, then production efficiency increases and costs decrease, but processing complexity increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidprocessing complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The method changes physical parameters of the semiconductor material through controlled dislocation formation and stress film deposition. By modifying crystal structure parameters and inducing controlled defects, the process achieves effective stressor formation at scaled dimensions without proportionally increasing processing complexity

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

A stress film serves as an intermediary element that mediates between the implantation process and the final stressor region formation. This intermediate layer enables controlled stress induction and crystallization without requiring direct complex processing of the active device regions, simplifying the overall fabrication approach

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances carrier mobility and stress levels in the channel region, improving device performance while minimizing manufacturing costs and utilizing existing manufacturing processes.

Implementation Method 1

A method involving a series of pre-amorphous implantation and annealing processes with stress film deposition and removal is employed to form bi-layer dislocations in the source and drain regions

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Implementation Method 2

A method involving a series of pre-amorphous implantation and annealing processes with stress film deposition and removal is employed to form bi-layer dislocations

Methodology Applied
Scientific EffectAnnealing: Annealing

Data Source

PatentUS9178063B2Semiconductor device
Publication Date: 2015.11.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9178063B2 patent drawing
  • US9178063B2 patent drawing
  • US9178063B2 patent drawing

AI summary

A semiconductor device includes a gate structure over a substrate, a source region in the substrate, where the source region is adjacent to the gate structure. Additionally, the semiconductor device includes a drain region in the substrate, where the drain region is adjacent to the gate structure. Moreover, the semiconductor device includes a first dislocation in the substrate between the source region and the drain region. Furthermore, the semiconductor device includes a second dislocation in the substrate between the source region and the drain region, where the second dislocation is substantially parallel to the first dislocation.