Bi-Layer Template for Semiconductor Via Structure
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Solution Overview
Problem
In semiconductor fabrication, the use of alternative metals in sub-10 nanometer process nodes leads to electron scattering and conductivity losses due to structural imperfections, and the integration of these metals with low-k dielectric materials results in mechanical weakness and line wiggling issues, causing damage and variability in metal structures.
Innovation Solution
A bi-layer template comprising a titanium nitride (TiN) layer and a low-k dielectric layer is used to mitigate line wiggling and reduce variability in metal dimensions, with the TiN layer providing a high modulus to resist thermal stresses and the low-k dielectric minimizing damage during etching, while allowing for the integration of alternative metals like copper and other refractory metals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If alternative metals are used in sub-10 nanometer process nodes, then electron scattering effects are reduced, but conductivity losses occur due to structural imperfections
Solution Approach 1:
The patent changes the material parameter by transitioning from copper to alternative metals (Ru, Co, Rh, Ir, Mo, Ni) with shorter mean free path lengths, which reduces electron scattering effects at nanoscale dimensions despite the presence of structural imperfections
Solution Approach 2:
The patent employs composite material structures including refractory metal liners (tantalum, tungsten) combined with alternative metals, and uses bi-layer templates (TiN and low-k dielectric) to achieve both mechanical strength and electrical performance in sub-10 nanometer processes
2Strength
If alternative metals are integrated with low-k dielectric materials, then mechanical weakness is reduced, but line wiggling issues cause damage and variability in metal structures
Solution Approach 1:
The patent segments the template structure into bi-layers: a TiN layer providing high modulus for mechanical strength and a low-k dielectric layer minimizing etching damage, thereby addressing both mechanical weakness and manufacturing precision requirements
Solution Approach 2:
The patent creates a composite template structure combining TiN (high elastic modulus ~440 GPa) with low-k dielectric materials, where each material compensates for the other's deficiencies - TiN provides mechanical strength while low-k dielectric reduces etching damage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bi-layer template effectively reduces line wiggling, minimizes damage to low-k dielectric materials, and achieves consistent metal line and via dimensions, enhancing the performance and reliability of integrated circuits by stabilizing the metal structures and reducing etching-related damage.
Implementation Method 1
the TiN layer providing a high modulus to resist thermal stresses
Implementation Method 2
minimizing damage during etching
Data Source
AI summary
An exemplary semiconductor structure includes a substrate defining a first trench; a first refractory metal liner coating the first trench; a heavy metal liner coating the first refractory metal liner; a copper structure filling the first trench over the heavy metal liner; a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer, wherein the low-k dielectric layer defines a second trench; a second refractory metal liner coating the second trench; a metal line filling the second refractory metal liner; and a metal via protruding from the metal line.