Integrated Bias Cell Layout for Compact Well and Substrate Biasing
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Solution Overview
Problem
As semiconductor processes advance and device sizes in integrated circuits are reduced, various limitations occur due to the smaller device sizes, necessitating an efficient structure for protecting or driving the devices.
Innovation Solution
The integrated circuit includes bias cells with a reduced area, comprising a plurality of wells and doped regions of specific conductivity types, alternately disposed to efficiently bias the substrate and wells, thereby reducing the overall area and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If device sizes are reduced to advance semiconductor processes, then integration density is improved, but various limitations and reliability issues occur
Solution Approach 1:
The biasing function is segmented into multiple distributed bias cells rather than using a single centralized bias structure. Each bias cell independently biases a local region, providing granular control and reducing the impact of defects on overall circuit reliability while maintaining compact device sizes.
Solution Approach 2:
Bias cells act as intermediary structures between the substrate/wells and the functional devices. These intermediary bias cells provide controlled potential to the substrate and wells, enabling proper device operation and protecting against reliability issues that arise from direct device-substrate interactions at scaled dimensions.
2Reliability
If traditional bias structures are used, then device biasing is achieved, but large area is occupied
Solution Approach 1:
The bias cells merge multiple functions into a compact structure: substrate biasing, well biasing, and leakage current control are integrated into a single cell design. This merging allows the biasing function to be distributed across multiple small cells rather than requiring a large centralized bias structure.
Solution Approach 2:
The bias cells are arranged in a distributed pattern across the substrate plane, utilizing spatial distribution in another dimension rather than concentrating biasing in a single location. This dimensional distribution reduces the peak area requirement while maintaining effective biasing coverage across the entire circuit.
Data Source
AI summary
An integrated circuit may include: a plurality of wells extending in parallel with each other in a first direction on a substrate having a first conductivity type, the plurality of wells having a second conductivity type; a plurality of first doped regions disposed on the plurality of wells in a first region and a second region, the first region being separated from the second region in the first direction, the plurality of first doped regions having the first conductivity type; a plurality of second doped regions disposed on the substrate between the plurality of wells in the first region and the second region and having the second conductivity type; and a plurality of third doped regions disposed in a third region of the substrate between the first region and the second region and having the first conductivity type.