Bias Circuit Back-Gate Control for Low-Voltage Drain Modulation
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Solution Overview
Problem
Current bias circuits for power amplifiers in cellular phone units operating on multiple frequency bands face challenges in controlling current at low voltages and addressing the drain modulation effect, leading to inefficiencies and increased circuit size.
Innovation Solution
A bias circuit design incorporating an operational amplifier, four-terminal FETs with back-gate terminals, and a current mirror circuit that utilizes the back-gate effect to control the threshold voltage of P-type FETs, allowing for low-voltage operation and current control reflecting changes in drain voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a cascode current mirror circuit is used to cancel the drain modulation effect, then the drain modulation effect is reduced, but the circuit size increases and the minimum acceptable voltage increases
Solution Approach 1:
The patent changes the electrical parameters of the FETs by applying different potentials to the back-gate terminals. By adjusting the back-gate potential, the threshold voltage of the FETs is modified to compensate for the drain modulation effect, achieving current accuracy without increasing circuit size or minimum voltage requirements
Solution Approach 2:
The patent replaces the structural solution (cascode configuration) with an electrical control solution (back-gate voltage adjustment). Instead of using additional FETs in a cascode arrangement to physically cancel the drain modulation effect, the invention uses electrical field control through the back-gate to modify FET characteristics and achieve the same compensation effect
2Object-affected harmful factors
If a cascode current mirror circuit is used to cancel the drain modulation effect, then the drain modulation effect is reduced, but the minimum acceptable voltage increases
Solution Approach 1:
The patent modifies the threshold voltage parameter of the FETs through back-gate control, enabling the circuit to operate accurately at lower voltages. By dynamically adjusting the back-gate potential, the FETs maintain proper operation even when the supply voltage is reduced, thus lowering the minimum acceptable voltage compared to cascode circuits
3Ease of operation
If the threshold voltage of FETs is not controlled, then the circuit operation is simple, but the current control accuracy deteriorates due to drain modulation effect
Solution Approach 1:
The patent implements a feedback mechanism where the drain voltage is monitored and used to control the back-gate potential of the FETs. This feedback loop automatically adjusts the threshold voltage to compensate for drain modulation effects, maintaining current control accuracy while keeping the overall circuit operation relatively simple through automated compensation
Solution Approach 2:
The patent replaces complex structural solutions with electrical control mechanisms. By using the back-gate terminal to electrically control the threshold voltage, the system achieves precise current control without requiring additional circuitry or complex configurations, thus maintaining operational simplicity while improving accuracy
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables reliable low-voltage operation and effective current control, reducing power consumption and increasing the operational margin of the bias circuit while minimizing the drain modulation effect.
Implementation Method 1
FETs configuring the current mirror circuit are a four-terminal type having a back-gate terminal, and the back-gate terminals of the FETs are at the same potential
Data Source
AI summary
There is provided a bias circuit that can operate even at low voltage and control a current reflecting a change in drain voltage. A first current mirror circuit for feeding back a drain terminal current of an FET which receives an output of an operational amplifier at a gate terminal to an input terminal of the operational amplifier and a second current mirror circuit are coupled in parallel. A variable voltage is coupled to the first current mirror circuit, and a fixed voltage is coupled to the second current mirror circuit. Even if the variable voltage becomes lower than the threshold voltage of FETs configuring the first current mirror circuit, the second current mirror circuit feeds back the current to the input terminal of the operational amplifier with reliability.