Bias Circuit Charge Sharing for Fast Low-Power Start-Up
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Solution Overview
Problem
Bias circuits in low power electronics, such as current references and current mirrors, experience long start-up periods due to settling of bias voltage levels, leading to inefficiencies and potential energy wastage, with existing techniques either disabling current flow or complicating circuit design.
Innovation Solution
A bias circuit design incorporating a first and second transistor, along with a switch array, that enables charge-sharing between parasitic capacitances to establish bias voltages quickly, with modes of operation to selectively couple transistors to supply voltage or ground, and programmable switches for precise control of final bias voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional techniques disable the bias circuit to cut current flow, then power consumption is reduced, but start-up time becomes excessively long due to charging node capacitances from zero
Solution Approach 1:
The patent applies preliminary action by pre-charging the node capacitances to appropriate voltage levels before the bias circuit is fully enabled. During the disabled state, capacitors maintain charge on critical nodes rather than allowing them to discharge to zero, so when the circuit is re-enabled, the capacitances are already near their target values, dramatically reducing the settling time required to establish proper bias voltages.
2Loss of time
If NMOS gate voltages are pulled to supply voltage and PMOS gate voltages to ground with separate transistors, then start-up time is reduced, but start-up current becomes many decades greater than final bias current, wasting energy
Solution Approach 1:
The patent applies partial action by using the separate transistor technique only temporarily during the initial charging phase, then transitioning to a more balanced operating mode. The circuit initially charges capacitances quickly using the low-impedance path, but once charging is complete, it settles into a state where the bias currents are much closer to their final values, avoiding sustained excessive current draw while maintaining fast start-up capability.
3Loss of energy
If node voltages are made to float to preserve charge, then some energy is preserved, but voltages drift off mark and start-up length becomes highly dependent on parameters like duty cycle and temperature
Solution Approach 1:
The patent applies feedback by continuously monitoring the bias node voltages and adjusting the charging/discharging actions accordingly. The circuit includes mechanisms to detect when nodes have drifted from their target voltages and applies corrective charging or discharging pulses to bring them back into the proper range, ensuring stable and reliable operation across varying duty cycles and temperatures while still preserving energy by avoiding unnecessary charging cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces start-up time and power consumption by utilizing existing capacitive charges, ensuring quicker establishment of bias voltages and minimizing energy wastage, while maintaining circuit stability and usability.
Implementation Method 1
the parasitic capacitance of the gates will be charged to a voltage representing full conduction
Implementation Method 2
enables charge-sharing between parasitic capacitances to establish bias voltages quickly
Data Source
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AI summary
A bias circuit is provided. The bias circuit may include a first transistor forming an input node, a second transistor forming an output node, and a switch array disposed between the first transistor and the second transistor. The switch array may be configured to charge the first transistor to a supply voltage and the second transistor to a ground during a first mode of operation, and couple the first transistor to the second transistor to approximate a final bias voltage during a second mode of operation.