Bias Generation Circuit for Buffer Delay Compensation

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Solution Overview

Problem

Semiconductor buffer circuits face challenges in maintaining consistent signal delay times due to variations in power voltage levels, which affect the timing of output signals.

Innovation Solution

A bias generation circuit is introduced, comprising a bias generator and compensator, which generates and controls a bias voltage based on a reference voltage and detects power voltage level changes to compensate for signal delay variations, ensuring consistent output signal timing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the power voltage level is higher than the target level, then the delay time of the output signal is decreased, but the timing consistency of the buffer circuit deteriorates

Engineering Contradiction:

Improvesignal delay timeVSAvoidtiming consistency

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent employs a feedback mechanism where the bias voltage is adjusted based on the detected power voltage level. The bias generation circuit continuously monitors the power voltage and modifies the bias voltage accordingly to maintain consistent signal delay times, resolving the timing consistency issue caused by power voltage variations

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The patent changes the bias voltage parameter in response to power voltage level changes. By dynamically adjusting the bias voltage based on the detected power voltage level, the system compensates for delay time variations and maintains timing consistency across different operating conditions

Inventive Principle:

Principle #35Parameter changes

2Speed

If the power voltage level is lower than the target level, then the delay time of the output signal is increased, but the timing consistency of the buffer circuit deteriorates

Engineering Contradiction:

Improvesignal delay timeVSAvoidtiming consistency

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The feedback mechanism detects when the power voltage level is lower than the target level and automatically adjusts the bias voltage to compensate for the increased delay time, thereby maintaining timing consistency despite the lower power voltage condition

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The bias voltage parameter is dynamically changed in response to detected power voltage levels. When power voltage is lower, the bias voltage is adjusted to offset the delay increase, ensuring timing consistency is maintained across varying power conditions

Inventive Principle:

Principle #35Parameter changes

3Reliability

If a bias generation circuit with compensator is added to control bias voltage based on power voltage detection, then the timing consistency is improved, but the device complexity increases

Engineering Contradiction:

Improvetiming consistencyVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the bias generation function with the power voltage detection and compensation functions into a single integrated bias generation circuit. This combination achieves timing consistency improvement while minimizing the increase in device complexity by consolidating multiple functions into one circuit block

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS11418170B2Bias generation circuit, buffer circuit including the bias generation circuit and semiconductor system including the buffer circuit

Publication Date: 2022.08.16 SK HYNIX INC

AI summary

A bias generation circuit may include a bias generator and compensator. The bias generator may be configured to generate a bias voltage based on a reference voltage. The compensator may be configured to detect level changes of a power voltage. The compensator may be configured to control a level of the bias voltage based on detection results.