Bias Circuit with Opposite Polarity MOSFETs for Voltage Stability
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Solution Overview
Problem
Amplification apparatuses are susceptible to variations in MOSFET characteristics due to manufacturing process variations, leading to significant deviations in output voltage, especially when p-type and n-type MOSFETs with different threshold voltage characteristics are used in source follower and amplification stages.
Innovation Solution
A bias circuit that includes a first and second voltage outputting unit, each comprising a current source and a voltage dropping portion with a MOSFET of opposite polarity, and a voltage comparator to equalize output voltages from these units, thereby supplying a bias voltage that compensates for the characteristics of both p-type and n-type MOSFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional bias circuit with a single polarity MOSFET is used, then the circuit structure is simple, but the output voltage deviates significantly due to process variations in MOSFET characteristics
Solution Approach 1:
The patent combines both p-type and n-type MOSFETs in the bias circuit to compensate for process variations. Specifically, the bias circuit includes a p-type MOSFET (P61) and an n-type MOSFET (N61) connected in series, where the gate voltages are coupled together. This merging of opposite polarity MOSFETs allows their characteristic variations to compensate each other, reducing the overall impact of process variations on the output voltage of the amplification apparatus.
Solution Approach 2:
The patent changes the parameter composition of the bias circuit by introducing both p-type and n-type MOSFETs with different threshold voltage characteristics. The bias voltage is generated based on the combined characteristics of these MOSFETs, where the gate-source voltages of both types are coupled together. This parameter diversification allows the bias circuit to compensate for process variations that affect single-polarity MOSFETs, thereby improving output voltage stability without significantly increasing circuit complexity.
2Productivity
If p-type and n-type MOSFETs with different threshold voltage characteristics are used in source follower and amplification stages, then the amplification performance is improved, but the output voltage becomes highly sensitive to process variations
Solution Approach 1:
The patent implements a feedback mechanism where the gate voltages of the p-type MOSFET (P61) and n-type MOSFET (N61) in the bias circuit are coupled together. This coupling creates a feedback loop that automatically adjusts the bias voltage to compensate for process variations. When process variations cause threshold voltage shifts in the MOSFETs of the amplification stages, the feedback mechanism in the bias circuit detects these changes and adjusts the bias voltage accordingly, maintaining output voltage stability while preserving amplification performance.
Solution Approach 2:
The patent uses a composite structure in the bias circuit by combining p-type and n-type MOSFETs with different threshold voltage characteristics. This composite approach leverages the complementary properties of opposite polarity MOSFETs, where their characteristic variations tend to compensate each other. The bias voltage is generated from this composite structure, providing stable operation despite process variations affecting the individual MOSFETs in the amplification stages.
Data Source
AI summary
An amplification apparatus includes a bias circuit for supplying a bias voltage, and an amplification circuit to which the bias voltage is supplied from the bias circuit. The bias circuit includes a first current source for increasing/decreasing a first current depending on the bias voltage, and a first MOSFET with first polarity through which the first current flows, to output a first voltage from a connection between the first current source and the first MOSFET; a second current source for outputting a constant current as a second current, and a second MOSFET with second polarity through which the second current flows, to output a second voltage from a connection between the second current source and the second MOSFET; and a voltage comparator for increasing/decreasing the bias voltage such that the first and second voltages become equal, based on a difference between the first and second voltages.