Bias Circuitry for Cascode Transistor Circuits
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Solution Overview
Problem
Existing bias voltage generating circuits for cascode transistors in integrated circuits fail to provide optimal biasing for transistors of different technology types, leading to varying bias voltages with temperature, process, and power supply variations, and are often physically larger and more costly due to the use of single or stacked diode-connected transistors and resistive dividers.
Innovation Solution
A composite transistor circuit is designed, comprising transistors of different technology types, where a first transistor of one technology type is coupled with a second transistor of another technology type, with a bias current forced through them to produce a bias voltage that tracks the intrinsic properties of both, ensuring optimal biasing across a range of parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If single or stacked diode-connected transistors are used to generate bias voltage, then the bias voltage can be generated, but the bias voltage varies widely with temperature, process, and power supply variations
Solution Approach 1:
The patent combines multiple transistors of different technology types (first technology type and second technology type) into a composite transistor structure. This merging allows the bias voltage generation circuit to track the intrinsic properties of both cascode and signal transistors simultaneously, resolving the contradiction between voltage stability and adaptability to different transistor characteristics
Solution Approach 2:
The patent uses a composite transistor structure comprising transistors of different technology types (different threshold voltages, different breakdown voltages). This composite structure generates a bias voltage that inherently tracks the properties of both transistor types, providing stable biasing across varying conditions while adapting to different intrinsic properties
2Strength
If stacked diode-connected transistors or resistive voltage dividers are used to generate large bias voltages, then the needed bias voltage magnitude can be achieved, but the circuit area increases and manufacturing costs increase
Solution Approach 1:
The patent merges multiple transistors into a composite structure that generates large bias voltages without requiring physical stacking or external resistive dividers. The composite transistor configuration achieves the needed voltage magnitude while occupying minimal chip area, directly addressing the contradiction between voltage strength and area consumption
Solution Approach 2:
The patent uses the composite transistor structure to generate bias voltages that are proportional to the intrinsic properties of the transistors being biased. This copying approach eliminates the need for separate voltage generation circuits, reducing overall circuit area while maintaining the required bias voltage magnitude
3Device complexity
If transistors of the same technology type are used in bias voltage generation, then the circuit is simpler, but it cannot effectively track characteristics of transistors of different technology types
Solution Approach 1:
The patent employs a composite transistor structure that intentionally combines transistors of different technology types. This composite approach increases circuit complexity slightly but enables effective tracking of characteristics for both cascode and signal transistors of different technology types, resolving the contradiction between simplicity and adaptability
Solution Approach 2:
The composite transistor structure serves multiple functions: it generates bias voltage, tracks intrinsic properties of different transistor types, and provides stable operation across varying conditions. This multi-functionality justifies the increased complexity by delivering comprehensive adaptability to different technology types
Data Source
AI summary
An integrated circuit includes a composite transistor including at least a first transistor of a first technology type having a first group of intrinsic properties and a second transistor of a second technology type having a second group of the intrinsic properties, at least one of the intrinsic properties of the second group being substantially different than a corresponding intrinsic property of the first group, the second transistor having a first electrode coupled to a supply voltage, a second electrode coupled to a first electrode of the first transistor, and a control electrode coupled to a bias voltage conductor and also coupled to a control electrode and a second electrode of the first transistor. A source of bias current is coupled to the bias voltage conductor and is also coupled to the second electrode of the second transistor. A bias voltage across the composite transistor is produced on the bias voltage conductor to bias a cascode transistor of the first technology type. A signal transistor of the second technology type is coupled to the first electrode of the cascode transistor.