Clock Data Recovery Bias Control for Noise and Frequency Offset
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Solution Overview
Problem
Conventional clock data recovery devices are limited by the bandwidth of their low-pass filters, which restricts their ability to reduce noise and track larger frequency offsets, especially in severe environment conditions such as rapid temperature changes.
Innovation Solution
A clock data recovery apparatus comprising an oscillator, a sampler circuit, and a frequency control circuit that generates a bias voltage through integration calculation, digital-to-analog conversion, and low-pass filtering using two different driving paths with varying gains and low-pass filter bandwidths to generate a bias voltage, enabling wider tracking range and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the low-pass filter is implemented with a wider bandwidth, then the clock data recovery device can track larger frequency offset, but it cannot reduce more noise
Solution Approach 1:
The patent divides the frequency control circuit into two separate driving paths: a first driving path with a first low-pass filter having a first bandwidth, and a second driving path with a second low-pass filter having a second bandwidth. Each path processes the sampling signal independently with different filtering characteristics, allowing the system to simultaneously achieve noise reduction and frequency offset tracking capability.
Solution Approach 2:
The patent applies different low-pass filter bandwidths to different parts of the system. The first low-pass filter uses a first bandwidth optimized for one aspect (noise reduction), while the second low-pass filter uses a second bandwidth optimized for another aspect (tracking capability). This local differentiation allows each path to excel at its specific function while working together to resolve the overall contradiction.
2Object-affected harmful factors
If the low-pass filter is implemented with a narrower bandwidth, then the clock data recovery device can reduce more noise, but it cannot track larger frequency offset
Solution Approach 1:
The system segments the signal processing into two parallel paths with different low-pass filter bandwidths. The first path uses a narrower bandwidth for superior noise reduction, while the second path uses a wider bandwidth for better tracking of large frequency offsets. Both paths contribute to the overall system performance.
Solution Approach 2:
The patent merges the outputs of two driving paths with different low-pass filter characteristics into a unified frequency control mechanism. By combining the results from both paths, the system achieves both noise reduction capability (from the narrower bandwidth path) and frequency offset tracking capability (from the wider bandwidth path).
Data Source
AI summary
A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.