Bias Current Feedback Circuit for Low-Noise Inverter Amplifiers
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Solution Overview
Problem
Inverter amplifiers require a low-noise bias current to maintain performance across process, voltage, and temperature (PVT) variations, but existing solutions are energy inefficient and prone to noise, especially due to their poor power supply rejection ratio (PSRR).
Innovation Solution
A bias circuit that provides a controlled bias current to the load circuit portion by regulating the bias voltage using a feedback loop, ensuring the bias current is proportional to the input current, thus isolating the bias voltage from the supply voltage and minimizing noise and jitter. This is achieved by using matched transistors with specific M-factor ratios to replicate the load transistor's characteristics, allowing for predictable PVT variations and reduced input current requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large current is drawn from the power supply through a configurable current divider to generate a controlled bias current, then the bias current control is achieved, but the energy efficiency deteriorates
Solution Approach 1:
The patent implements a feedback mechanism where the bias circuit monitors the actual bias current drawn from the power supply and dynamically adjusts the current division ratio to maintain the desired bias current level. This closed-loop control ensures accurate bias current regulation while minimizing the total current drawn from the power supply, thereby resolving the contradiction between reliability and energy efficiency.
Solution Approach 2:
The patent dynamically changes the resistance values or current division ratios in the bias circuit based on operating conditions such as temperature, process variations, and load requirements. By adjusting these parameters in real-time, the circuit maintains optimal bias current control while minimizing power consumption across different operating scenarios, thus resolving the contradiction between reliable bias control and energy efficiency.
2Device complexity
If the bias voltage is directly connected to the power supply to simplify the circuit, then the device complexity is reduced, but the noise level increases due to poor power supply rejection ratio
Solution Approach 1:
The patent introduces an intermediary bias circuit between the power supply and the inverter amplifier that acts as a buffer and filter. This intermediary circuit includes voltage regulation and noise filtering components that isolate the sensitive inverter amplifier from power supply noise while maintaining simple overall circuit architecture, thus resolving the contradiction between device complexity and noise level.
3Reliability
If existing bias control circuits are used to maintain performance across PVT variations, then the performance consistency is improved, but the additional current consumption increases
Solution Approach 1:
The patent implements a self-service bias control mechanism where the bias circuit automatically compensates for PVT variations using intrinsic circuit elements and feedback loops without requiring external control signals or additional current sources. The circuit self-adjusts its operating point based on temperature and process variations, maintaining performance consistency while minimizing additional current consumption beyond the essential bias current itself.
Data Source
Figure 1
AI summary
A circuit portion (1) comprises a load circuit portion (4) and a bias circuit portion (6). The load circuit portion (4) comprises a load transistor (46). The bias circuit portion (4) comprises a replica transistor (24) matched to the load transistor (46) and connected to the load transistor (46) at a node (34) such that when a current flows through the replica transistor (24), a current proportional to the current through the replica transistor (24) flows through the load transistor (46). The bias circuit portion also comprises a current input (18) for receiving an input current (Ibias), a supply voltage input (10) for receiving a supply voltage (VDDA), and a feedback loop arranged to: adjust a voltage (Vreg) at the node (34) connecting the replica transistor (24) and the load transistor (46) such that the replica transistor (24) conducts a current proportional to the input current (Ibias), and counteract variations in the voltage (Vreg) at the node (34) connecting the replica transistor (24) and the load transistor (46) arising from changes in the supply voltage (VDDA).