Bias Current Circuit Using Sub-Threshold NMOS for Temperature Stability
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Solution Overview
Problem
Existing circuits for generating bias current are sensitive to temperature, leading to inaccurate output currents, which affects the stability of electronic circuits and systems.
Innovation Solution
A circuit design incorporating a loop unit with PMOS and NMOS transistors operating in a sub-threshold region, an amplifying unit to compensate for gain variations, and a resistor unit with a temperature-dependent resistance, which generates a bias current that is less sensitive to temperature fluctuations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If NMOS transistors operate in saturation region with conventional current mirror structure, then current clamping function is achieved, but output bias current becomes highly sensitive to temperature
Solution Approach 1:
The patent changes the operating region parameter of NMOS transistors from saturation region to sub-threshold region. This parameter change fundamentally alters the transistor characteristics, enabling the output bias current to become insensitive to temperature variations while maintaining current stability through the unique properties of sub-threshold operation
2Temperature
If amplifying unit is added to compensate gain variations, then temperature sensitivity is reduced, but circuit complexity increases
Solution Approach 1:
The patent introduces an amplifying unit that forms a feedback loop to compensate for gain variations caused by temperature changes. The amplifying unit continuously adjusts the bias current based on detected variations, creating a closed-loop system that actively counteracts temperature effects and maintains stable output current
Data Source
AI summary
A circuit for generating a bias current is provided, including: a loop unit, which includes a first current mirror structure constituted by a first PMOS transistor and a second PMOS transistor, and a second current mirror structure constituted by a first NMOS transistor and a second NMOS transistor, where the first and second NMOS transistors operate in a sub-threshold region; an output unit, adapted to output the bias current; and an amplifying unit, which includes a first input terminal and an output terminal, where the first input terminal is connected with a source of the first NMOS transistor or a source of the second NMOS transistor, and the output terminal is connected with gates of both the first and the second PMOS transistors. The bias current output from the circuit may be not sensitive to temperatures.