Bias-Controlled Delay Cell for Low-Jitter Delay Lines
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Solution Overview
Problem
Semiconductor delay lines with multiple delay cells are sensitive to variations in power and ground voltages, leading to increased jitter and waveform distortion.
Innovation Solution
Incorporating three-phase inverters in parallel with delay elements, which receive bias voltages to compensate for voltage variations, thereby stabilizing the delay operation and reducing jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of selected delay cells is increased to increase the delay amount, then the delay time is extended, but the waveform becomes more sensitive to power source voltage variations and jitter increases
Solution Approach 1:
The patent introduces bias voltage control to dynamically adjust the operating parameters of delay cells. By changing the bias voltage applied to delay elements, the delay time can be adjusted without increasing the number of delay cells, thereby maintaining waveform stability while achieving the desired delay amount.
Solution Approach 2:
The patent replaces the mechanical approach of adding more delay cells (increasing physical quantity) with an electrical control approach using bias voltages. Instead of increasing the number of components, the invention uses voltage control to achieve delay adjustment, substituting a complex structural solution with a simpler parameter-based solution.
2Loss of time
If the number of selected delay cells is increased to increase the delay amount, then the delay time is extended, but jitter increases and distorts the input signal waveform
Solution Approach 1:
The patent uses bias voltage as a control parameter to adjust delay time continuously without discrete steps. This parameter change approach allows for smooth delay adjustment while maintaining signal integrity, avoiding the jitter that occurs when multiple delay cells are cascaded.
Solution Approach 2:
The patent introduces dynamic control of delay elements through bias voltage adjustment. The delay time becomes a dynamic parameter that can be adjusted in real-time without changing the physical structure or number of delay cells, enabling flexible delay control while maintaining waveform quality.
Data Source
AI summary
A delay cell includes: a plurality of delay elements coupled in series; and at least one three-phase inverter that is coupled in parallel to at least one of the delay elements, and that receives through a first control terminal a first bias voltage for compensating for a variation of a power source voltage, and receives through a second control terminal a second bias voltage for compensating for a variation of a ground voltage.