Bias-Insensitive Trigger Circuit for BigFET ESD Protection

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Solution Overview

Problem

Conventional ESD protection circuits for IC chips deteriorate when system-level ESD pulses are applied during a powered state due to pre-bias voltage, necessitating a trigger device for bigFET-based ESD protection that functions regardless of the IC chip's power status.

Innovation Solution

A bigFET-based ESD protection device with a trigger circuit comprising a slew rate detector, driver stage, and keep-on latch, where the driver stage is kept on with a driving voltage insensitive to pre-bias on the bigFET's drain or source terminal, ensuring the ESD protection circuit operates effectively whether the IC is powered or unpowered.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional trigger circuit is used for bigFET-based ESD protection, then the circuit can operate during unpowered state, but the performance deteriorates when ESD pulse is applied during powered state due to pre-bias voltage

Engineering Contradiction:

ImproveESD protection capability across power statesVSAvoidtrigger circuit performance under pre-bias condition

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The trigger circuit performs preliminary action by detecting the ESD pulse through the slew rate detector before the pre-bias voltage can affect the driver stage. The keep-on latch is activated in advance to maintain the driver stage in a conducting state throughout the ESD event, ensuring the bigFET is properly triggered regardless of pre-bias conditions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The keep-on latch acts as an intermediary between the slew rate detector and the driver stage. It decouples the driver stage from direct influence by the pre-bias voltage on the bigFET, using the latch's internal circuitry to maintain proper triggering signals independent of the bigFET's bias state.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If the driver stage is directly connected to bigFET gate, then the circuit is simple, but the driving voltage becomes sensitive to pre-bias on drain or source terminal

Engineering Contradiction:

Improvetrigger circuit structureVSAvoiddriving voltage stability under pre-bias

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The trigger circuit is segmented into distinct functional blocks: slew rate detector, keep-on latch, and driver stage. This segmentation isolates the driver stage from direct exposure to pre-bias voltage effects on the bigFET, allowing each block to perform its function independently and reliably.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The keep-on latch serves as an intermediary stage between the detection circuitry and the driver stage. It processes the ESD detection signal and maintains the driver stage activation without being directly affected by the pre-bias voltage conditions on the bigFET terminals.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If keep-on latch maintains driver stage activated, then ESD protection is ensured during powered state, but additional circuit components are required

Engineering Contradiction:

ImproveESD protection under powered stateVSAvoidtrigger device structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The keep-on latch combines multiple functions into a single circuit block: it latches the ESD detection signal, maintains the driver stage activation, and ensures continuous drive to the bigFET gate throughout the ESD event. This merging of functions achieves reliable ESD protection while minimizing the overall circuit complexity.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The keep-on latch is designed to perform multiple functions: detecting ESD events through the slew rate detector, maintaining driver stage activation during the ESD pulse, and ensuring proper bigFET operation regardless of pre-bias conditions. This multi-functionality provides robust ESD protection across both powered and unpowered states.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP2840608B1A bias-insensitive trigger circuit for bigfet esd supply protection

Publication Date: 2017.08.30 NXP BV

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AI summary

Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, an ESD protection device for an integrated circuit (IC) device includes a bigFET configured to conduct an ESD current during an ESD event and a trigger device configured to trigger the bigFET during the ESD event. The trigger device includes a slew rate detector configured to detect the ESD event, a driver stage configured to drive the bigFET, and a keep-on latch configured to keep the driver stage turned on to drive a gate terminal of the bigFET with a driving voltage that is insensitive to a pre-bias on a drain terminal or a source terminal of the bigFET. Other embodiments are also described.