Bias Current Receiver Selective Coupling Against Gate Antenna Damage
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Solution Overview
Problem
Integrated circuits (ICs) face the challenge of gate antenna effect during manufacturing, where metal traces can damage field effect transistors (FETs) due to accumulated electrical charges, leading to decreased yield and potential failure.
Innovation Solution
Incorporating a selective coupling circuit that selectively couples the drain of a first FET to the gates of both the first and second FETs based on the voltage at the drain of the first FET, preventing direct coupling of metal traces to the gates and thus mitigating the gate antenna effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the metal trace is coupled directly to the gates of the current mirror FETs, then the reference current can be transmitted to the bias current receiver, but gate antenna effect occurs causing charges to discharge through the gate oxide and damage the FETs
Solution Approach 1:
The patent introduces an intermediate coupling mechanism between the metal trace and the FET gates. Instead of direct coupling, the reference current is transmitted through an intermediate structure that prevents charge accumulation on the metal trace from discharging through the gate oxide, thereby eliminating the gate antenna effect while maintaining current transmission functionality.
Solution Approach 2:
The coupling path is segmented into distinct sections: the metal trace, an intermediate coupling structure, and the FET gates. This segmentation isolates the gate oxide from the metal trace, preventing the harmful discharge path while allowing the reference current to be transmitted through the intermediate structure to the bias current receiver.
2Ease of manufacture
If the metal trace is coupled directly to the gates, then the circuit structure is simple, but manufacturing yield decreases due to FET damage from gate antenna effect
Solution Approach 1:
The intermediate coupling structure is designed to be integrated into the standard CMOS fabrication process, adding minimal complexity to the manufacturing workflow. The structure serves as a mediator that prevents FET damage during manufacturing, thereby improving yield without significantly complicating the ease of manufacture.
3Ease of operation
If the metal trace is coupled directly to the gates, then the current mirror operation can be effected, but the FETs may fail due to charge discharge through the gate oxide
Solution Approach 1:
The intermediate coupling structure enables the current mirror operation to proceed while simultaneously protecting the FETs from failure. The intermediary allows the reference current to reach the bias current receiver for proper current mirror functionality, while preventing the harmful discharge path that would cause FET failure.
Data Source
AI summary
An integrated circuit (IC), including: a current mirror, including: a first field effect transistor (FET) including a first drain, a first gate, and a first source, wherein the first source is coupled to a first voltage rail; and a second FET including a second drain, a second gate, and a second source, wherein the second gate is coupled to the first gate of the first FET, and the second source is coupled to the first voltage rail; and a selective coupling circuit configured to selectively couple the first drain of the first FET to the first and second gates of the first and second FETs based on a voltage at the first drain of the first FET.