Bias Receiver Circuit for High-to-Low Voltage Analog Nodes

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Solution Overview

Problem

Circuit nodes operating at different voltage levels face challenges in efficiently communicating and maintaining reliability due to the use of thin-oxide devices, particularly when analog nodes need to operate at higher voltages and are interconnected to lower voltage domains.

Innovation Solution

A bias receiver and protection device configuration is employed, where the protection device is coupled to a lower voltage domain level, allowing current to pass through when in a non-collapse mode and blocking current flow when in a collapse mode, utilizing a diode stack to manage voltage levels and prevent reliability issues.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If analog nodes operate at higher voltage for better dynamic performance, then dynamic performance is improved, but reliability deteriorates due to thin-oxide device limitations and voltage level incompatibility

Engineering Contradiction:
ImprovereliabilityVSAvoiddynamic performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent introduces a bias receiver circuit as an intermediary component between high-voltage analog nodes and low-voltage digital domains. This bias receiver receives bias currents from the high-voltage domain, conditions them through transistors operating in specific regions, and provides regulated bias signals to low-voltage circuits. This intermediary approach allows high-voltage analog circuits to operate at higher voltages for improved dynamic performance while protecting low-voltage domains from voltage incompatibility and reliability issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If voltage translation is implemented between different voltage levels, then adaptability is improved, but device complexity increases due to additional translation circuits

Engineering Contradiction:
Improvevoltage level compatibilityVSAvoidcircuit complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The bias receiver circuit performs multiple functions within a single integrated structure: it provides voltage level translation, current regulation, bias generation for multiple circuits, and protection between voltage domains. By consolidating these functions into one universal circuit block rather than separate dedicated circuits for each function, the patent achieves voltage level compatibility across different domains while minimizing the increase in overall device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If protection devices are added to manage voltage levels, then reliability is improved, but area overhead increases

Engineering Contradiction:
Improvevoltage level protectionVSAvoidcircuit area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the protection device functionality with the bias receiver circuit operations. The transistors within the bias receiver serve dual purposes: they perform the primary function of bias current regulation and voltage level translation, while simultaneously acting as protection devices that prevent high-voltage signals from damaging low-voltage circuits. This merging eliminates the need for separate dedicated protection circuits, thereby improving reliability through voltage level protection without incurring additional area overhead.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS12445124B2Voltage aware bias receiver in an analog node
Publication Date: 2025.10.14 QUALCOMM INC
  • US12445124B2 patent drawing
  • US12445124B2 patent drawing
  • US12445124B2 patent drawing

AI summary

An apparatus, including: an input node; a bias receiver; and a protection device, a gate of the protection device coupled to the bias receiver, the bias receiver tied to a lower voltage domain level, a first source or drain of the protection device coupled to the input node to receive a current from an analog node or a higher voltage domain level from the analog node and a second drain or source of the protection device coupled to a current output node, when the current is received through the input node to the protection device and the lower voltage domain level is in a non-collapse mode, configured to pass the current through the protection device to the current output node.